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Quantum computing : circuits, systems, automation and applications / / edited by Himanshu Thapliyal, Travis Humble
| Quantum computing : circuits, systems, automation and applications / / edited by Himanshu Thapliyal, Travis Humble |
| Pubbl/distr/stampa | Cham : , : Springer, , [2024] |
| Descrizione fisica | 1 online resource (290 pages) : illustrations |
| Disciplina | 006.3843 |
| Soggetto topico |
Electronic circuits
Quantum computing Embedded computer systems Electronic circuit design Electronic Circuits and Systems Quantum Information Embedded Systems Electronics Design and Verification |
| ISBN |
3-031-37966-7
9783031379666 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Quantum Computing -- Quantum Circuit Synthesis -- Quantum Arithmetic Circuits -- Quantum Resource Estimation -- Quantum Compiler and Programming Languages -- Validation and Testing in Quantum Computing -- Quantum Computing Security -- Applications of Quantum Computing to fields such as Quantum Chemistry, Linear Algebra, Scientific Applications, Material Science, Machine Learning, etc. -- Quantum Technologies: Superconducting, Trapped Ions, Spintronics, Cryogenic Electronics for Quantum Computing. |
| Record Nr. | UNINA-9910766891503321 |
| Cham : , : Springer, , [2024] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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System on Chip (SOC) Architecture [[electronic resource] ] : A Practical Approach / / by Veena S. Chakravarthi, Shivananda R. Koteshwar
| System on Chip (SOC) Architecture [[electronic resource] ] : A Practical Approach / / by Veena S. Chakravarthi, Shivananda R. Koteshwar |
| Autore | Chakravarthi Veena S. |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (174 pages) |
| Disciplina | 605 |
| Soggetto topico |
Electrical engineering
Embedded computer systems Electronic circuits Electronic circuit design Electronics Electrical and Electronic Engineering Embedded Systems Electronic Circuits and Systems Electronics Design and Verification Electronics and Microelectronics, Instrumentation |
| ISBN | 3-031-36242-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | SoC Abstractions and Technology -- SoC Types and Its Constituents -- System Modelling and Chip Architecture -- Embedded Processors -- SOC Memory -- SOC Design Flow -- Advanced SOC Architectures -- System Verification -- Self-Assessment Question Bank. |
| Record Nr. | UNINA-9910741160803321 |
Chakravarthi Veena S.
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
| Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
| Autore | Zamiri Azar Kimia |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (385 pages) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
Mardani KamaliHadi
FarahmandiFarimah TehranipoorMark |
| Soggetto topico |
Electronic circuit design
Embedded computer systems Electronic circuits Electronics Design and Verification Embedded Systems Electronic Circuits and Systems |
| ISBN | 3-031-37989-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. |
| Record Nr. | UNINA-9910760263503321 |
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Zamiri Azar Kimia
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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