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Advanced Boolean Techniques [[electronic resource] ] : Selected Papers from the 15th International Workshop on Boolean Problems / / edited by Rolf Drechsler, Sebastian Huhn
| Advanced Boolean Techniques [[electronic resource] ] : Selected Papers from the 15th International Workshop on Boolean Problems / / edited by Rolf Drechsler, Sebastian Huhn |
| Autore | Drechsler Rolf |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (174 pages) |
| Disciplina | 621.3815 |
| Altri autori (Persone) | HuhnSebastian |
| Soggetto topico |
Electronic circuits
Computer science - Mathematics Embedded computer systems Electronic circuit design Electronic Circuits and Systems Mathematical Applications in Computer Science Embedded Systems Electronics Design and Verification |
| Soggetto non controllato | Mathematics |
| ISBN | 3-031-28916-1 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Arithmetic Satisfiability-Modulo-Theory Solving Applied to Non-Standard Analysis Problems of Cyber-Physical Systems -- Chapter 2. Fast AIG-based Approximate Logic Synthesis -- Chapter 3. External Don’t Cares in Logic Synthesis -- Chapter 4. Maiorana-McFarland Boolean Bent Functions Characterized by their Reed-Muller Spectra -- Chapter 5. Towards System-level Assertions for Heterogeneous Systems -- Chapter 6. SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms -- Chapter 7. Autosymmetric and D-reducible Functions: Theory and Application to Security -- Chapter 8. Two-operands modular multiplication to small bit-ranges -- Chapter 9. Low Latency Real-Time Inference for Multilayer Perceptrons on FPGAs -- Chapter 10. Thirty-six Officers of Euler - New Insights Computed Using XBOOLE -- Chapter 11. Start Small but Dream Big: On Choosing a Static Variable Order for Multiplier BDDs. |
| Record Nr. | UNINA-9910728387303321 |
Drechsler Rolf
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi
| Hardware Security Primitives [[electronic resource] /] / by Mark Tehranipoor, Nitin Pundir, Nidish Vashistha, Farimah Farahmandi |
| Autore | Tehranipoor Mohammad H. <1974-> |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (356 pages) |
| Disciplina | 929.605 |
| Soggetto topico |
Electronic circuits
Electronic circuit design Microprocessors Computer architecture Electronic Circuits and Systems Electronics Design and Verification Processor Architectures |
| ISBN | 3-031-19185-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Hardware Security Primitives and their Applications -- Racetrack PUF -- TERO PUF -- Direct Characterization PUF -- Volatile Memory Based PUF -- Emerging Memory Based PUF -- Extrinsic Characterization of PUF -- Radio PUFs and CoAs -- Optical PUFs -- True Random Number Generators -- Hardware Camouflaging -- Temper Detection Methods -- Embedded Watermarking -- Counterfeit and Recycled IC Detection -- Package-Level Counterfeit IC Detection -- Side Channels Protection in Cryptographic Hardware -- Fault Injection Resistant Cryptographic Hardware -- Energy and Performance Optimization for Cryptography -- Lightweight Cryptography -- Post-Quantum Cryptography -- Virtual Proof of Reality -- Analog Security. |
| Record Nr. | UNINA-9910635396903321 |
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Tehranipoor Mohammad H. <1974->
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi
| Hardware Security Training, Hands-on! [[electronic resource] /] / by Mark Tehranipoor, N. Nalla Anandakumar, Farimah Farahmandi |
| Autore | Tehranipoor Mark |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (XXIV, 320 p. 250 illus., 218 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Embedded computer systems Electronic circuit design Electronic Circuits and Systems Embedded Systems Electronics Design and Verification |
| ISBN | 3-031-31034-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Chapter 1. Physical Unclonable Functions (PUFs) -- Chapter 2. True Random Number Generator (TRNG) -- Chapter 3. Recycled Chip Detection using RO-based Odometer -- Chapter 4. Recycled FPGA Detection -- Chapter 5. Hardware Trojan Insertion -- Chapter 6. Hardware Trojan Detection -- Chapter 7. Security Verification -- Chapter 8. Power Analysis Attacks on AES -- Chapter 9. EM Side-Channel Attack on AES -- Chapter 10. Logic Locking Insertion and Assessment -- Chapter 11. Clock Glitch Fault Attack on FSM in AES Controller -- Chapter 12. Voltage Glitch Attack on an FPGA AES Implementation -- Chapter 13. Laser Fault Injection Attack (FIA) -- Chapter 14. Optical Probing Attack on Logic Locking -- Chapter 15. Universal Fault Sensor -- Chapter 16. Scanning Electron Microscope Training. |
| Record Nr. | UNINA-9910742492103321 |
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Tehranipoor Mark
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Polynomial Formal Verification of Approximate Functions [[electronic resource] /] / by Martha Schnieber
| Polynomial Formal Verification of Approximate Functions [[electronic resource] /] / by Martha Schnieber |
| Autore | Schnieber Martha |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Wiesbaden : , : Springer Fachmedien Wiesbaden : , : Imprint : Springer Vieweg, , 2023 |
| Descrizione fisica | 1 online resource (87 pages) |
| Disciplina | 512.942 |
| Collana | BestMasters |
| Soggetto topico |
Electronic circuits
Electronic circuit design Algebra Mathematics - Data processing Electronic Circuits and Systems Electronics Design and Verification Computational Mathematics and Numerical Analysis |
| ISBN | 3-658-41888-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Preliminaries -- RelatedWork -- PolynomialVerification -- Experiments -- Conclusion. |
| Record Nr. | UNINA-9910735787803321 |
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Schnieber Martha
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| Wiesbaden : , : Springer Fachmedien Wiesbaden : , : Imprint : Springer Vieweg, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems [[electronic resource] /] / by Behnaz Ranjbar, Alireza Ejlali, Akash Kumar
| Quality-of-Service Aware Design and Management of Embedded Mixed-Criticality Systems [[electronic resource] /] / by Behnaz Ranjbar, Alireza Ejlali, Akash Kumar |
| Autore | Ranjbar Behnaz |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (205 pages) |
| Disciplina | 006.22 |
| Altri autori (Persone) |
EjlaliAlireza
KumarAkash |
| Soggetto topico |
Electronic circuits
Embedded computer systems Electronic circuit design Electronic Circuits and Systems Embedded Systems Electronics Design and Verification |
| ISBN | 3-031-38960-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Preliminaries and Literature Reviews -- Bounding Time in Mixed-Criticality Systems -- Safety- and Task-Drop-Aware Mixed-Criticality Task Scheduling -- Learning-Based Drop-Aware Mixed-Criticality Task Scheduling -- Fault-Tolerance and Power-Aware Multi-Core Mixed-Criticality System Design -- QoS- and Power-Aware Run-Time Scheduler for Multi-Core Mixed-Criticality Systems -- Conclusion. |
| Record Nr. | UNINA-9910760267403321 |
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Ranjbar Behnaz
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Quantum computing : circuits, systems, automation and applications / / edited by Himanshu Thapliyal, Travis Humble
| Quantum computing : circuits, systems, automation and applications / / edited by Himanshu Thapliyal, Travis Humble |
| Pubbl/distr/stampa | Cham : , : Springer, , [2024] |
| Descrizione fisica | 1 online resource (290 pages) : illustrations |
| Disciplina | 006.3843 |
| Soggetto topico |
Electronic circuits
Quantum computing Embedded computer systems Electronic circuit design Electronic Circuits and Systems Quantum Information Embedded Systems Electronics Design and Verification |
| ISBN |
3-031-37966-7
9783031379666 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to Quantum Computing -- Quantum Circuit Synthesis -- Quantum Arithmetic Circuits -- Quantum Resource Estimation -- Quantum Compiler and Programming Languages -- Validation and Testing in Quantum Computing -- Quantum Computing Security -- Applications of Quantum Computing to fields such as Quantum Chemistry, Linear Algebra, Scientific Applications, Material Science, Machine Learning, etc. -- Quantum Technologies: Superconducting, Trapped Ions, Spintronics, Cryogenic Electronics for Quantum Computing. |
| Record Nr. | UNINA-9910766891503321 |
| Cham : , : Springer, , [2024] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Security of FPGA-Accelerated Cloud Computing Environments [[electronic resource] /] / edited by Jakub Szefer, Russell Tessier
| Security of FPGA-Accelerated Cloud Computing Environments [[electronic resource] /] / edited by Jakub Szefer, Russell Tessier |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (X, 328 p. 187 illus., 157 illus. in color.) |
| Disciplina | 621.3815 |
| Soggetto topico |
Electronic circuits
Electronic circuit design Cooperating objects (Computer systems) Electronic Circuits and Systems Electronics Design and Verification Cyber-Physical Systems |
| ISBN | 3-031-45395-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction to, and history of, Cloud FPGAs -- FPGA device level security issues and countermeasures -- FPGA interfacing security issues (buses attacks, memory interfaces, etc -- IP protection for FPGAs in the cloud -- Software system security for cloud FPGAs (hypervisor leaks, shared memory use) -- Cross-node/network security – (e.g., voltage attack across nodes, network flooding by FPGAs) -- Likely future attacks -- Summary and conclusion. |
| Record Nr. | UNINA-9910799231803321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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System on Chip (SOC) Architecture [[electronic resource] ] : A Practical Approach / / by Veena S. Chakravarthi, Shivananda R. Koteshwar
| System on Chip (SOC) Architecture [[electronic resource] ] : A Practical Approach / / by Veena S. Chakravarthi, Shivananda R. Koteshwar |
| Autore | Chakravarthi Veena S. |
| Edizione | [1st ed. 2023.] |
| Pubbl/distr/stampa | Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 |
| Descrizione fisica | 1 online resource (174 pages) |
| Disciplina | 605 |
| Soggetto topico |
Electrical engineering
Embedded computer systems Electronic circuits Electronic circuit design Electronics Electrical and Electronic Engineering Embedded Systems Electronic Circuits and Systems Electronics Design and Verification Electronics and Microelectronics, Instrumentation |
| ISBN | 3-031-36242-X |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | SoC Abstractions and Technology -- SoC Types and Its Constituents -- System Modelling and Chip Architecture -- Embedded Processors -- SOC Memory -- SOC Design Flow -- Advanced SOC Architectures -- System Verification -- Self-Assessment Question Bank. |
| Record Nr. | UNINA-9910741160803321 |
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Chakravarthi Veena S.
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| Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
| Understanding Logic Locking [[electronic resource] /] / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
| Autore | Zamiri Azar Kimia |
| Edizione | [1st ed. 2024.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 |
| Descrizione fisica | 1 online resource (385 pages) |
| Disciplina | 005.8 |
| Altri autori (Persone) |
Mardani KamaliHadi
FarahmandiFarimah TehranipoorMark |
| Soggetto topico |
Electronic circuit design
Embedded computer systems Electronic circuits Electronics Design and Verification Embedded Systems Electronic Circuits and Systems |
| ISBN | 3-031-37989-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP. |
| Record Nr. | UNINA-9910760263503321 |
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Zamiri Azar Kimia
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| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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