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FDL 2010 : 2010 Forum on Specification & Design Languages : 14-16 September 2010
| FDL 2010 : 2010 Forum on Specification & Design Languages : 14-16 September 2010 |
| Pubbl/distr/stampa | New York : , : IEEE, , 2011 |
| Descrizione fisica | 1 online resource (220 pages) |
| Soggetto topico |
Software engineering
Computer hardware description languages Computer software - Verification |
| ISBN |
2-9530504-4-2
2-9530504-3-4 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910141214303321 |
| New York : , : IEEE, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li
| Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li |
| Autore | Tsai Jeffrey J.-P |
| Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific, c2001 |
| Descrizione fisica | 1 online resource (228 p.) |
| Disciplina | 004.35 |
| Altri autori (Persone) | LiBing <1960-> |
| Collana | Series on software engineering and knowledge engineering |
| Soggetto topico |
Computer hardware description languages
System design |
| Soggetto genere / forma | Electronic books. |
| ISBN | 981-279-796-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Contents; 1 Introduction; 2 Current Approaches; 2.1 Data Dependency Analysis; 2.2 OR-Parallelism; 2.3 AND-Parallelism; 2.4 Backtracking; 3 Overview of the New Approach; 3.1 Non-monotonic Inheritance Expansion; 3.2 Static Data Dependency Analysis; 3.3 Automatic Transformation; 3.4 Hybrid AND-OR Parallel Execution; 3.5 Simplified OR-Parallel Model; 3.6 Backtracking Elimination; 4 FRORL Requirements Specification Language and Its Decomposition; 4.1 Knowledge Representation through Object-Oriented Model; 4.2 The Modeling Primitives of FRORL; 4.3 Decomposition of a FRORL Requirements Specification
5 Rewriting and Data Dependency Control Flow Analysis of a Logic-Based Specification5.1 Rewriting of a Logic-Based Specification; 5.2 Data Dependency and Control Flow Analysis; 6 Hybrid AND-OR Parallelism Implementation; 6.1 The Usage of Mode Information in the Parallel Model; 6.2 AND-OR Parallel Execution; 6.3 Synchronization in OR-Parallel Execution Model; 6.4 Calculation of the Currently Executable Predicate Set; 6.5 Hybrid Execution Algorithm; 6.6 Comparison with the Conventional BFS and DFS; 6.7 Advantages of the New Approach 6.8 Analysis of Non-functional Requirements in the New Parallel Execution Model7 Efficiency Considerations and Experimental Results; 7.1 Execution Evaluation; 7.2 Communication Evaluation; 7.3 Criteria for Simulation and Ealuation; 7.4 A Simulator for Parallel Logic-based Specification Evaluation; 7.5 Experimental Results and Comparison; 8 Mode Information Support for Automatic Transformation System; 8.1 Architecture of a Logic-based Specification Transformation System; 8.2 Determination of Control Sequence; 8.3 Data Type Generation and Procedural Function Formation 8.4 Intelligent Backtracking for Transformation System9 Describing Non-Functional Requirements in FRORL; 9.1 Functional Requirements vs. Non-functional Requirements; 9.2 Issues in Non-functional Requirements; 9.3 Non-functional Requirements Modeling in FRORL; 9.4 Adjusting Non-functional Requirements; 10 Summary |
| Record Nr. | UNINA-9910453552703321 |
Tsai Jeffrey J.-P
|
||
| Singapore ; ; New Jersey, : World Scientific, c2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li
| Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li |
| Autore | Tsai Jeffrey J.-P |
| Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific, c2001 |
| Descrizione fisica | 1 online resource (228 p.) |
| Disciplina | 004.35 |
| Altri autori (Persone) | LiBing <1960-> |
| Collana | Series on software engineering and knowledge engineering |
| Soggetto topico |
Computer hardware description languages
System design |
| ISBN | 981-279-796-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Contents; 1 Introduction; 2 Current Approaches; 2.1 Data Dependency Analysis; 2.2 OR-Parallelism; 2.3 AND-Parallelism; 2.4 Backtracking; 3 Overview of the New Approach; 3.1 Non-monotonic Inheritance Expansion; 3.2 Static Data Dependency Analysis; 3.3 Automatic Transformation; 3.4 Hybrid AND-OR Parallel Execution; 3.5 Simplified OR-Parallel Model; 3.6 Backtracking Elimination; 4 FRORL Requirements Specification Language and Its Decomposition; 4.1 Knowledge Representation through Object-Oriented Model; 4.2 The Modeling Primitives of FRORL; 4.3 Decomposition of a FRORL Requirements Specification
5 Rewriting and Data Dependency Control Flow Analysis of a Logic-Based Specification5.1 Rewriting of a Logic-Based Specification; 5.2 Data Dependency and Control Flow Analysis; 6 Hybrid AND-OR Parallelism Implementation; 6.1 The Usage of Mode Information in the Parallel Model; 6.2 AND-OR Parallel Execution; 6.3 Synchronization in OR-Parallel Execution Model; 6.4 Calculation of the Currently Executable Predicate Set; 6.5 Hybrid Execution Algorithm; 6.6 Comparison with the Conventional BFS and DFS; 6.7 Advantages of the New Approach 6.8 Analysis of Non-functional Requirements in the New Parallel Execution Model7 Efficiency Considerations and Experimental Results; 7.1 Execution Evaluation; 7.2 Communication Evaluation; 7.3 Criteria for Simulation and Ealuation; 7.4 A Simulator for Parallel Logic-based Specification Evaluation; 7.5 Experimental Results and Comparison; 8 Mode Information Support for Automatic Transformation System; 8.1 Architecture of a Logic-based Specification Transformation System; 8.2 Determination of Control Sequence; 8.3 Data Type Generation and Procedural Function Formation 8.4 Intelligent Backtracking for Transformation System9 Describing Non-Functional Requirements in FRORL; 9.1 Functional Requirements vs. Non-functional Requirements; 9.2 Issues in Non-functional Requirements; 9.3 Non-functional Requirements Modeling in FRORL; 9.4 Adjusting Non-functional Requirements; 10 Summary |
| Record Nr. | UNINA-9910782275703321 |
|
Tsai Jeffrey J.-P
|
||
| Singapore ; ; New Jersey, : World Scientific, c2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li
| Hybrid parallel execution model for logic-based specification languages [[electronic resource] /] / Jeffrey J.P. Tsai, Bing Li |
| Autore | Tsai Jeffrey J.-P |
| Pubbl/distr/stampa | Singapore ; ; New Jersey, : World Scientific, c2001 |
| Descrizione fisica | 1 online resource (228 p.) |
| Disciplina | 004.35 |
| Altri autori (Persone) | LiBing <1960-> |
| Collana | Series on software engineering and knowledge engineering |
| Soggetto topico |
Computer hardware description languages
System design |
| ISBN | 981-279-796-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Contents; 1 Introduction; 2 Current Approaches; 2.1 Data Dependency Analysis; 2.2 OR-Parallelism; 2.3 AND-Parallelism; 2.4 Backtracking; 3 Overview of the New Approach; 3.1 Non-monotonic Inheritance Expansion; 3.2 Static Data Dependency Analysis; 3.3 Automatic Transformation; 3.4 Hybrid AND-OR Parallel Execution; 3.5 Simplified OR-Parallel Model; 3.6 Backtracking Elimination; 4 FRORL Requirements Specification Language and Its Decomposition; 4.1 Knowledge Representation through Object-Oriented Model; 4.2 The Modeling Primitives of FRORL; 4.3 Decomposition of a FRORL Requirements Specification
5 Rewriting and Data Dependency Control Flow Analysis of a Logic-Based Specification5.1 Rewriting of a Logic-Based Specification; 5.2 Data Dependency and Control Flow Analysis; 6 Hybrid AND-OR Parallelism Implementation; 6.1 The Usage of Mode Information in the Parallel Model; 6.2 AND-OR Parallel Execution; 6.3 Synchronization in OR-Parallel Execution Model; 6.4 Calculation of the Currently Executable Predicate Set; 6.5 Hybrid Execution Algorithm; 6.6 Comparison with the Conventional BFS and DFS; 6.7 Advantages of the New Approach 6.8 Analysis of Non-functional Requirements in the New Parallel Execution Model7 Efficiency Considerations and Experimental Results; 7.1 Execution Evaluation; 7.2 Communication Evaluation; 7.3 Criteria for Simulation and Ealuation; 7.4 A Simulator for Parallel Logic-based Specification Evaluation; 7.5 Experimental Results and Comparison; 8 Mode Information Support for Automatic Transformation System; 8.1 Architecture of a Logic-based Specification Transformation System; 8.2 Determination of Control Sequence; 8.3 Data Type Generation and Procedural Function Formation 8.4 Intelligent Backtracking for Transformation System9 Describing Non-Functional Requirements in FRORL; 9.1 Functional Requirements vs. Non-functional Requirements; 9.2 Issues in Non-functional Requirements; 9.3 Non-functional Requirements Modeling in FRORL; 9.4 Adjusting Non-functional Requirements; 10 Summary |
| Record Nr. | UNINA-9910825441903321 |
|
Tsai Jeffrey J.-P
|
||
| Singapore ; ; New Jersey, : World Scientific, c2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2011 |
| Descrizione fisica | 1 online resource (1294 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-6607-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEC 62530 Edition 2.0 2011-05 IEEE Std 1800: SystemVerilog Unified Hardware Design, Specification, and Verification Language |
| Record Nr. | UNINA-9910135406503321 |
| Piscataway, New Jersey : , : IEEE, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers
| IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers |
| Pubbl/distr/stampa | Piscataway, New Jersey : , : IEEE, , 2011 |
| Descrizione fisica | 1 online resource (1294 pages) |
| Disciplina | 621.392 |
| Soggetto topico |
Verilog (Computer hardware description language)
Computer hardware description languages |
| ISBN | 0-7381-6607-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | IEC 62530 Edition 2.0 2011-05 IEEE Std 1800: SystemVerilog Unified Hardware Design, Specification, and Verification Language |
| Record Nr. | UNISA-996279343203316 |
| Piscataway, New Jersey : , : IEEE, , 2011 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE ABBET Standard for Test Equipment Description Language (TEDL): 993-1997
| IEEE ABBET Standard for Test Equipment Description Language (TEDL): 993-1997 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 1997 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.392 |
| Soggetto topico |
Computer hardware description languages
ATLAS (Computer program language) |
| ISBN | 0-7381-3754-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910147095303321 |
| [Place of publication not identified], : IEEE, 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEEE ABBET Standard for Test Equipment Description Language (TEDL): 993-1997
| IEEE ABBET Standard for Test Equipment Description Language (TEDL): 993-1997 |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 1997 |
| Descrizione fisica | 1 online resource |
| Disciplina | 621.392 |
| Soggetto topico |
Computer hardware description languages
ATLAS (Computer program language) |
| ISBN | 0-7381-3754-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996281027203316 |
| [Place of publication not identified], : IEEE, 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
IEEE Standard VHDL Analog and Mixed-Signal Extensions
| IEEE Standard VHDL Analog and Mixed-Signal Extensions |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 1999 |
| Descrizione fisica | 1 online resource (303 pages) |
| Disciplina | 621.392 |
| Collana | Institute of Electrical and Electronics Engineers |
| Soggetto topico | Computer hardware description languages |
| ISBN | 0-7381-1641-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910142217503321 |
| [Place of publication not identified], : IEEE, 1999 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
IEEE Standard VHDL Analog and Mixed-Signal Extensions
| IEEE Standard VHDL Analog and Mixed-Signal Extensions |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE, 1999 |
| Descrizione fisica | 1 online resource (303 pages) |
| Disciplina | 621.392 |
| Collana | Institute of Electrical and Electronics Engineers |
| Soggetto topico | Computer hardware description languages |
| ISBN | 0-7381-1641-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280511303316 |
| [Place of publication not identified], : IEEE, 1999 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
