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Computer Vision – ACCV 2018 Workshops [[electronic resource] ] : 14th Asian Conference on Computer Vision, Perth, Australia, December 2–6, 2018, Revised Selected Papers / / edited by Gustavo Carneiro, Shaodi You
| Computer Vision – ACCV 2018 Workshops [[electronic resource] ] : 14th Asian Conference on Computer Vision, Perth, Australia, December 2–6, 2018, Revised Selected Papers / / edited by Gustavo Carneiro, Shaodi You |
| Edizione | [1st ed. 2019.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
| Descrizione fisica | 1 online resource (XV, 541 p. 260 illus., 230 illus. in color.) |
| Disciplina | 006.37 |
| Collana | Image Processing, Computer Vision, Pattern Recognition, and Graphics |
| Soggetto topico |
Optical data processing
Artificial intelligence Computer organization Computer hardware Image Processing and Computer Vision Artificial Intelligence Computer Systems Organization and Communication Networks Computer Hardware |
| ISBN | 3-030-21074-X |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Scene Understanding and Modelling (SUMO) Challenge -- Learning and Inference Methods for High Performance Imaging (LIMHPI) -- Attention/Intention Understanding (AIU) -- Museum Exhibit Identification Challenge (Open MIC) for Domain Adaptation and Few-Shot Learning -- RGB-D - Sensing and Understanding via Combined Colour and Depth -- Dense 3D Reconstruction for Dynamic Scenes -- AI Aesthetics in Art and Media (AIAM) -- Robust Reading (IWRR), Artificial Intelligence for Retinal Image Analysis (AIRIA) -- Combining Vision and Language, Advanced Machine Vision for Real-life and Industrially Relevant Applications (AMV). |
| Record Nr. | UNISA-996466287503316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Concurrency and Hardware Design [[electronic resource] ] : Advances in Petri Nets / / edited by Jordi Cortadella, Alex Yakovlev, Grzegorz Rozenberg
| Concurrency and Hardware Design [[electronic resource] ] : Advances in Petri Nets / / edited by Jordi Cortadella, Alex Yakovlev, Grzegorz Rozenberg |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 |
| Descrizione fisica | 1 online resource (X, 346 p.) |
| Disciplina | 004/.35 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Software engineering
Computer hardware Computer organization Computers Mathematical logic Software Engineering/Programming and Operating Systems Computer Hardware Computer Systems Organization and Communication Networks Software Engineering Computation by Abstract Devices Mathematical Logic and Formal Languages |
| ISBN | 3-540-36190-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Formal Models -- Composing Snippets -- A Programming Approach to the Design of Asynchronous Logic Blocks -- Asynchronous Circuits -- GALA (Globally Asynchronous — Locally Arbitrary) Design -- Synthesis of Reactive Systems: Application to Asynchronous Circuit Design -- Decomposition in Asynchronous Circuit Design -- Embedded System Design -- Functional and Performance Modeling of Concurrency in VCC -- Modeling and Designing Heterogeneous Systems -- Timed Verification and Performance Analysis -- Timed Verification of Asynchronous Circuits -- Performance Analysis of Asynchronous Circuits Using Markov Chains. |
| Record Nr. | UNINA-9910143889003321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Concurrency and Hardware Design [[electronic resource] ] : Advances in Petri Nets / / edited by Jordi Cortadella, Alex Yakovlev, Grzegorz Rozenberg
| Concurrency and Hardware Design [[electronic resource] ] : Advances in Petri Nets / / edited by Jordi Cortadella, Alex Yakovlev, Grzegorz Rozenberg |
| Edizione | [1st ed. 2002.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 |
| Descrizione fisica | 1 online resource (X, 346 p.) |
| Disciplina | 004/.35 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Software engineering
Computer hardware Computer organization Computers Mathematical logic Software Engineering/Programming and Operating Systems Computer Hardware Computer Systems Organization and Communication Networks Software Engineering Computation by Abstract Devices Mathematical Logic and Formal Languages |
| ISBN | 3-540-36190-1 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Formal Models -- Composing Snippets -- A Programming Approach to the Design of Asynchronous Logic Blocks -- Asynchronous Circuits -- GALA (Globally Asynchronous — Locally Arbitrary) Design -- Synthesis of Reactive Systems: Application to Asynchronous Circuit Design -- Decomposition in Asynchronous Circuit Design -- Embedded System Design -- Functional and Performance Modeling of Concurrency in VCC -- Modeling and Designing Heterogeneous Systems -- Timed Verification and Performance Analysis -- Timed Verification of Asynchronous Circuits -- Performance Analysis of Asynchronous Circuits Using Markov Chains. |
| Record Nr. | UNISA-996465748003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Concurrent Programming: Algorithms, Principles, and Foundations [[electronic resource] /] / by Michel Raynal
| Concurrent Programming: Algorithms, Principles, and Foundations [[electronic resource] /] / by Michel Raynal |
| Autore | Raynal Michel |
| Edizione | [1st ed. 2013.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 |
| Descrizione fisica | 1 online resource (528 p.) |
| Disciplina | 005.275 |
| Soggetto topico |
Computers
Computer organization Software engineering Computer hardware Theory of Computation Computer Systems Organization and Communication Networks Software Engineering/Programming and Operating Systems Computer Hardware |
| ISBN | 3-642-32027-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Part I - Lock-Based Synchronization -- Chap. 1 - The Mutual Exclusion Problem -- Chap. 2 - Solving Mutual Exclusion -- Chap. 3 - Lock-Based Concurrent Objects -- Part II - On the Foundations Side: The Atomicity Concept -- Chap. 4 - Atomicity: Formal Definition and Properties -- Part III - Mutex-Free Synchronization -- Chap. 5 - Mutex-Free Concurrent Objects -- Chap. 6 - Hybrid Concurrent Objects -- Chap. 7 - Wait-Free Objects from Read/Write Registers Only -- Chap. 8 - Snapshot Objects from Read/Write Registers Only -- Chap. 9 - Renaming Objects from Read/Write Registers Only -- Part IV - The Transactional Memory Approach -- Chap. 10 - Transactional Memory -- Part V - On the Foundations Side: From Safe Bits to Atomic Registers -- Chap. 11 - Safe, Regular and Atomic Read/Write Registers -- Chap. 12 - From Safe Bits to Atomic Bits: A Lower Bound and an Optimal Construction -- Chap. 13 - Bounded Constructions of Atomic b-Valued Registers -- Part VI - On the Foundations Side: The Computability Power of Concurrent Objects (Consensus) -- Chap. 14 - Universality of Consensus -- Chap. 15 - The Case of Unreliable Base Objects -- Chap. 16 - Consensus Numbers and the Consensus Hierarchy -- Chap. 17 - The Alphas and Omega of Consensus: Failure Detector-Based Consensus -- Afterword -- Bibliography -- Index. |
| Record Nr. | UNINA-9910437584803321 |
Raynal Michel
|
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| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2013 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Constructive Side-Channel Analysis and Secure Design [[electronic resource] ] : 7th International Workshop, COSADE 2016, Graz, Austria, April 14-15, 2016, Revised Selected Papers / / edited by François-Xavier Standaert, Elisabeth Oswald
| Constructive Side-Channel Analysis and Secure Design [[electronic resource] ] : 7th International Workshop, COSADE 2016, Graz, Austria, April 14-15, 2016, Revised Selected Papers / / edited by François-Xavier Standaert, Elisabeth Oswald |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (X, 219 p. 74 illus.) |
| Disciplina | 005.82 |
| Collana | Security and Cryptology |
| Soggetto topico |
Data encryption (Computer science)
Computer security Management information systems Computer science Algorithms Computer science—Mathematics Computer hardware Cryptology Systems and Data Security Management of Computing and Information Systems Algorithm Analysis and Problem Complexity Discrete Mathematics in Computer Science Computer Hardware |
| ISBN | 3-319-43283-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Security and Physical Attacks -- Exploiting the Physical Disparity: Side-Channel Attacks on Memory Encryption -- Co-location detection on the Cloud -- Simple Photonic Emission Attack with Reduced Data Complexity -- Side-Channel Analysis (case studies) -- Power Analysis Attacks against IEEE 802.15.4 Node -- Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series -- Dismantling real-world ECC with Horizontal and Vertical Template Attacks -- Fault Analysis -- Algorithmic Countermeasures Against Fault Attacks and Power Analysis for RSA-CRT -- Improved Differential Fault Analysis on Camellia-128 -- A Note on the Security of CHES 2014 Symmetric Infective Countermeasure -- Side-Channel Analysis (tools) -- Simpler, Faster, and More Robust T-test Based Leakage Detection -- Design and implementation of a waveform-matching based triggering system -- Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order. |
| Record Nr. | UNINA-9910484728403321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Constructive Side-Channel Analysis and Secure Design [[electronic resource] ] : 7th International Workshop, COSADE 2016, Graz, Austria, April 14-15, 2016, Revised Selected Papers / / edited by François-Xavier Standaert, Elisabeth Oswald
| Constructive Side-Channel Analysis and Secure Design [[electronic resource] ] : 7th International Workshop, COSADE 2016, Graz, Austria, April 14-15, 2016, Revised Selected Papers / / edited by François-Xavier Standaert, Elisabeth Oswald |
| Edizione | [1st ed. 2016.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
| Descrizione fisica | 1 online resource (X, 219 p. 74 illus.) |
| Disciplina | 005.82 |
| Collana | Security and Cryptology |
| Soggetto topico |
Data encryption (Computer science)
Computer security Management information systems Computer science Algorithms Computer science—Mathematics Computer hardware Cryptology Systems and Data Security Management of Computing and Information Systems Algorithm Analysis and Problem Complexity Discrete Mathematics in Computer Science Computer Hardware |
| ISBN | 3-319-43283-4 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Security and Physical Attacks -- Exploiting the Physical Disparity: Side-Channel Attacks on Memory Encryption -- Co-location detection on the Cloud -- Simple Photonic Emission Attack with Reduced Data Complexity -- Side-Channel Analysis (case studies) -- Power Analysis Attacks against IEEE 802.15.4 Node -- Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series -- Dismantling real-world ECC with Horizontal and Vertical Template Attacks -- Fault Analysis -- Algorithmic Countermeasures Against Fault Attacks and Power Analysis for RSA-CRT -- Improved Differential Fault Analysis on Camellia-128 -- A Note on the Security of CHES 2014 Symmetric Infective Countermeasure -- Side-Channel Analysis (tools) -- Simpler, Faster, and More Robust T-test Based Leakage Detection -- Design and implementation of a waveform-matching based triggering system -- Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order. |
| Record Nr. | UNISA-996465970503316 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Cooperative Environments for Distributed Systems Engineering [[electronic resource] ] : The Distributed Systems Environment Report / / by Khalil Drira, Andrea Martelli, Thierry Villemur
| Cooperative Environments for Distributed Systems Engineering [[electronic resource] ] : The Distributed Systems Environment Report / / by Khalil Drira, Andrea Martelli, Thierry Villemur |
| Autore | Drira Khalil |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (CCXCVI, 286 p.) |
| Disciplina | 004/.36 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Software engineering
Computer hardware User interfaces (Computer systems) Computer communication systems Management information systems Computer science Software Engineering/Programming and Operating Systems Computer Hardware User Interfaces and Human Computer Interaction Software Engineering Computer Communication Networks Management of Computing and Information Systems |
| ISBN | 3-540-45582-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cooperative Environments for Distributed System Engineering -- Research and Development Projects -- Relevant Existing Practices -- Middleware -- Product Data and Workflow Management -- Communications -- Groupware. |
| Record Nr. | UNISA-996466168803316 |
|
Drira Khalil
|
||
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Cooperative Environments for Distributed Systems Engineering [[electronic resource] ] : The Distributed Systems Environment Report / / by Khalil Drira, Andrea Martelli, Thierry Villemur
| Cooperative Environments for Distributed Systems Engineering [[electronic resource] ] : The Distributed Systems Environment Report / / by Khalil Drira, Andrea Martelli, Thierry Villemur |
| Autore | Drira Khalil |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (CCXCVI, 286 p.) |
| Disciplina | 004/.36 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Software engineering
Computer hardware User interfaces (Computer systems) Computer communication systems Management information systems Computer science Software Engineering/Programming and Operating Systems Computer Hardware User Interfaces and Human Computer Interaction Software Engineering Computer Communication Networks Management of Computing and Information Systems |
| ISBN | 3-540-45582-5 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Cooperative Environments for Distributed System Engineering -- Research and Development Projects -- Relevant Existing Practices -- Middleware -- Product Data and Workflow Management -- Communications -- Groupware. |
| Record Nr. | UNINA-9910767517303321 |
|
Drira Khalil
|
||
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Correct Hardware Design and Verification Methods [[electronic resource] ] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings / / edited by Daniel Geist, Enrico Tronci
| Correct Hardware Design and Verification Methods [[electronic resource] ] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings / / edited by Daniel Geist, Enrico Tronci |
| Edizione | [1st ed. 2003.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003 |
| Descrizione fisica | 1 online resource (XII, 432 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computers
Computer hardware Computer logic Software engineering Mathematical logic Artificial intelligence Theory of Computation Computer Hardware Logics and Meanings of Programs Software Engineering Mathematical Logic and Formal Languages Artificial Intelligence |
| ISBN | 3-540-39724-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- “More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques. |
| Record Nr. | UNINA-9910144023503321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Correct Hardware Design and Verification Methods [[electronic resource] ] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings / / edited by Daniel Geist, Enrico Tronci
| Correct Hardware Design and Verification Methods [[electronic resource] ] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings / / edited by Daniel Geist, Enrico Tronci |
| Edizione | [1st ed. 2003.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003 |
| Descrizione fisica | 1 online resource (XII, 432 p.) |
| Disciplina | 621.395 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Computers
Computer hardware Computer logic Software engineering Mathematical logic Artificial intelligence Theory of Computation Computer Hardware Logics and Meanings of Programs Software Engineering Mathematical Logic and Formal Languages Artificial Intelligence |
| ISBN | 3-540-39724-8 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- “More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques. |
| Record Nr. | UNISA-996465790003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Soggetto topico
-
Computer hardware
(208)
- Computer Hardware (206)
- Software engineering (72)
- Artificial Intelligence (53)
- Artificial intelligence (53)