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RACS '19 : Proceedings of the Conference on Research in Adaptive and Convergent Systems / / Chih-Cheng Hung [and six others]
| RACS '19 : Proceedings of the Conference on Research in Adaptive and Convergent Systems / / Chih-Cheng Hung [and six others] |
| Autore | Hung Chih-Cheng |
| Pubbl/distr/stampa | New York : , : Association for Computing Machinery, , 2019 |
| Descrizione fisica | 1 online resource (323 pages) |
| Disciplina | 004 |
| Collana | ACM international conference proceedings series |
| Soggetto topico |
Convergence (Telecommunication)
Adaptive computing systems |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910412334103321 |
Hung Chih-Cheng
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| New York : , : Association for Computing Machinery, , 2019 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass
| ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass |
| Pubbl/distr/stampa | New York : , : IEEE, , 2018 |
| Descrizione fisica | 1 online resource (183 pages) |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN | 1-5386-3797-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996280444303316 |
| New York : , : IEEE, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass
| ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 / / editors, Peter Athanas, René Cumplido, Claudia Feregrino, Ron Sass |
| Pubbl/distr/stampa | New York : , : IEEE, , 2018 |
| Descrizione fisica | 1 online resource (183 pages) |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN | 1-5386-3797-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910258254103321 |
| New York : , : IEEE, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ReConFig 2008 : proceedings : 2008 International Conference on Reconfigurable Computing and FPGAs : 3-5 December 2008, Cancun, Mexico
| ReConFig 2008 : proceedings : 2008 International Conference on Reconfigurable Computing and FPGAs : 3-5 December 2008, Cancun, Mexico |
| Pubbl/distr/stampa | New York : , : IEEE, , 2008 |
| Descrizione fisica | 1 online resource (460 pages) |
| Soggetto topico |
Field programmable gate arrays
Programmable array logic Adaptive computing systems |
| ISBN |
1-5090-7994-7
0-7695-3474-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910145411103321 |
| New York : , : IEEE, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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ReConFig 2008 : proceedings : 2008 International Conference on Reconfigurable Computing and FPGAs : 3-5 December 2008, Cancun, Mexico
| ReConFig 2008 : proceedings : 2008 International Conference on Reconfigurable Computing and FPGAs : 3-5 December 2008, Cancun, Mexico |
| Pubbl/distr/stampa | New York : , : IEEE, , 2008 |
| Descrizione fisica | 1 online resource (460 pages) |
| Soggetto topico |
Field programmable gate arrays
Programmable array logic Adaptive computing systems |
| ISBN |
1-5090-7994-7
0-7695-3474-0 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996214004103316 |
| New York : , : IEEE, , 2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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Reconfigurable computing [[electronic resource] ] : experiences and methodologies / / Song Jun Park, Dale Shires, and Brian Henz
| Reconfigurable computing [[electronic resource] ] : experiences and methodologies / / Song Jun Park, Dale Shires, and Brian Henz |
| Autore | Park Song Jun |
| Pubbl/distr/stampa | Aberdeen Proving Ground, MD : , : Army Research Laboratory, , [2008] |
| Descrizione fisica | 1 online resource (viii, 24 pages) : illustrations |
| Altri autori (Persone) |
ShiresDale R
HenzBrian J |
| Collana | ARL-TR |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays Computer architecture |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Altri titoli varianti | Reconfigurable computing |
| Record Nr. | UNINA-9910699085303321 |
|
Park Song Jun
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| Aberdeen Proving Ground, MD : , : Army Research Laboratory, , [2008] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon
| Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 |
| Descrizione fisica | 1 online resource (945 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
HauckScott
DeHonAndré |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-09615-6
9786611096151 0-08-055601-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Reconfigurable Computing; Copyright Page; Table of Contents; List of Contributors; Preface; Introduction; Part I: Reconfigurable Computing Hardware; Chapter 1. Device Architecture; 1.1 Logic-The Computational Fabric; 1.2 The Array and Interconnect; 1.3 Extending Logic; 1.4 Configuration; 1.5 Case Studies; 1.6 Summary; References; Chapter 2. Reconfigurable Computing Architectures; 2.1 Reconfigurable Processing Fabric Architectures; 2.2 RPF Integration into Traditional Computing Systems; 2.3 Summary and Future Work; References; Chapter 3. Reconfigurable Computing Systems
3.1 Early Systems3.2 PAM, VCC, and Splash; 3.3 Small-Scale Reconfigurable Systems; 3.4 Circuit Emulation; 3.5 Accelerating Technology; 3.6 Reconfigurable Supercomputing; 3.7 Non-FPGA Research; 3.8 Other System Issues; 3.9 The Future of Reconfigurable Systems; References; Chapter 4. Reconfiguration Management; 4.1 Reconfiguration; 4.2 Configuration Architectures; 4.3 Managing the Reconfiguration Process; 4.4 Reducing Configuration Transfer Time; 4.5 Configuration Security; 4.6 Summary; References; Part II: Programming Reconfigurable Systems; Chapter 5. Compute Models and System Architectures 5.1 Compute Models5.2 System Architectures; References; Chapter 6. Programming FPGA Applications in VHDL; 6.1 VHDL Programming; 6.2 Hardware Compilation Flow; 6.3 Limitations of VHDL; References; Chapter 7. Compiling C for Spatial Computing; 7.1 Overview of How C Code Runs on Spatial Hardware; 7.2 Automatic Compilation; 7.3 Uses and Variations of C Compilation to Hardware; 7.4 Summary; References; Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink; 8.1 Designing High-Performance Datapaths Using Stream-Based Operators; 8.2 An Image-Processing Design Driver 8.3 Specifying Control in Simulink8.4 Component Reuse: Libraries of Simple and Complex Subsystems; 8.5 Summary; References; Chapter 9. Stream Computations Organized for Reconfigurable Execution; 9.1 Programming; 9.2 System Architecture and Execution Patterns; 9.3 Compilation; 9.4 Runtime; 9.5 Highlights; References; Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model; 10.1 SIMD Computing on FPGAs: An Example; 10.2 SIMD Processing Architectures; 10.3 Data Parallel Languages; 10.4 Reconfigurable Computers for SIMD/Vector Processing 10.5 Variations of SIMD/Vector Computing10.6 Pipelined SIMD/Vector Processing; 10.7 Summary; References; Chapter 11. Operating System Support for Reconfigurable Computing; 11.1 History; 11.2 Abstracted Hardware Resources; 11.3 Flexible Binding; 11.4 Scheduling; 11.5 Communication; 11.6 Synchronization; 11.7 Protection; 11.8 Summary; References; Chapter 12. The JHDL Design and Debug System; 12.1 JHDL Background and Motivation; 12.2 The JHDL Design Language; 12.3 The JHDL CAD System; 12.4 JHDL'S Hardware Mode; 12.5 Advanced JHDL Capabilities; 12.6 Summary; References Part III: Mapping Designs to Reconfigurable Platforms |
| Record Nr. | UNINA-9910458407503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon
| Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 |
| Descrizione fisica | 1 online resource (945 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
HauckScott
DeHonAndré |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN |
1-281-09615-6
9786611096151 0-08-055601-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Reconfigurable Computing; Copyright Page; Table of Contents; List of Contributors; Preface; Introduction; Part I: Reconfigurable Computing Hardware; Chapter 1. Device Architecture; 1.1 Logic-The Computational Fabric; 1.2 The Array and Interconnect; 1.3 Extending Logic; 1.4 Configuration; 1.5 Case Studies; 1.6 Summary; References; Chapter 2. Reconfigurable Computing Architectures; 2.1 Reconfigurable Processing Fabric Architectures; 2.2 RPF Integration into Traditional Computing Systems; 2.3 Summary and Future Work; References; Chapter 3. Reconfigurable Computing Systems
3.1 Early Systems3.2 PAM, VCC, and Splash; 3.3 Small-Scale Reconfigurable Systems; 3.4 Circuit Emulation; 3.5 Accelerating Technology; 3.6 Reconfigurable Supercomputing; 3.7 Non-FPGA Research; 3.8 Other System Issues; 3.9 The Future of Reconfigurable Systems; References; Chapter 4. Reconfiguration Management; 4.1 Reconfiguration; 4.2 Configuration Architectures; 4.3 Managing the Reconfiguration Process; 4.4 Reducing Configuration Transfer Time; 4.5 Configuration Security; 4.6 Summary; References; Part II: Programming Reconfigurable Systems; Chapter 5. Compute Models and System Architectures 5.1 Compute Models5.2 System Architectures; References; Chapter 6. Programming FPGA Applications in VHDL; 6.1 VHDL Programming; 6.2 Hardware Compilation Flow; 6.3 Limitations of VHDL; References; Chapter 7. Compiling C for Spatial Computing; 7.1 Overview of How C Code Runs on Spatial Hardware; 7.2 Automatic Compilation; 7.3 Uses and Variations of C Compilation to Hardware; 7.4 Summary; References; Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink; 8.1 Designing High-Performance Datapaths Using Stream-Based Operators; 8.2 An Image-Processing Design Driver 8.3 Specifying Control in Simulink8.4 Component Reuse: Libraries of Simple and Complex Subsystems; 8.5 Summary; References; Chapter 9. Stream Computations Organized for Reconfigurable Execution; 9.1 Programming; 9.2 System Architecture and Execution Patterns; 9.3 Compilation; 9.4 Runtime; 9.5 Highlights; References; Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model; 10.1 SIMD Computing on FPGAs: An Example; 10.2 SIMD Processing Architectures; 10.3 Data Parallel Languages; 10.4 Reconfigurable Computers for SIMD/Vector Processing 10.5 Variations of SIMD/Vector Computing10.6 Pipelined SIMD/Vector Processing; 10.7 Summary; References; Chapter 11. Operating System Support for Reconfigurable Computing; 11.1 History; 11.2 Abstracted Hardware Resources; 11.3 Flexible Binding; 11.4 Scheduling; 11.5 Communication; 11.6 Synchronization; 11.7 Protection; 11.8 Summary; References; Chapter 12. The JHDL Design and Debug System; 12.1 JHDL Background and Motivation; 12.2 The JHDL Design Language; 12.3 The JHDL CAD System; 12.4 JHDL'S Hardware Mode; 12.5 Advanced JHDL Capabilities; 12.6 Summary; References Part III: Mapping Designs to Reconfigurable Platforms |
| Record Nr. | UNINA-9910784875803321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon
| Reconfigurable computing [[electronic resource] ] : the theory and practice of FPGA-based computation / / edited by Scott Hauck and André DeHon |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 |
| Descrizione fisica | 1 online resource (945 p.) |
| Disciplina | 621.39/5 |
| Altri autori (Persone) |
HauckScott
DeHonAndré |
| Collana | The Morgan Kaufmann series in systems on silicon |
| Soggetto topico |
Adaptive computing systems
Field programmable gate arrays |
| ISBN |
1-281-09615-6
9786611096151 0-08-055601-9 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Front Cover; Reconfigurable Computing; Copyright Page; Table of Contents; List of Contributors; Preface; Introduction; Part I: Reconfigurable Computing Hardware; Chapter 1. Device Architecture; 1.1 Logic-The Computational Fabric; 1.2 The Array and Interconnect; 1.3 Extending Logic; 1.4 Configuration; 1.5 Case Studies; 1.6 Summary; References; Chapter 2. Reconfigurable Computing Architectures; 2.1 Reconfigurable Processing Fabric Architectures; 2.2 RPF Integration into Traditional Computing Systems; 2.3 Summary and Future Work; References; Chapter 3. Reconfigurable Computing Systems
3.1 Early Systems3.2 PAM, VCC, and Splash; 3.3 Small-Scale Reconfigurable Systems; 3.4 Circuit Emulation; 3.5 Accelerating Technology; 3.6 Reconfigurable Supercomputing; 3.7 Non-FPGA Research; 3.8 Other System Issues; 3.9 The Future of Reconfigurable Systems; References; Chapter 4. Reconfiguration Management; 4.1 Reconfiguration; 4.2 Configuration Architectures; 4.3 Managing the Reconfiguration Process; 4.4 Reducing Configuration Transfer Time; 4.5 Configuration Security; 4.6 Summary; References; Part II: Programming Reconfigurable Systems; Chapter 5. Compute Models and System Architectures 5.1 Compute Models5.2 System Architectures; References; Chapter 6. Programming FPGA Applications in VHDL; 6.1 VHDL Programming; 6.2 Hardware Compilation Flow; 6.3 Limitations of VHDL; References; Chapter 7. Compiling C for Spatial Computing; 7.1 Overview of How C Code Runs on Spatial Hardware; 7.2 Automatic Compilation; 7.3 Uses and Variations of C Compilation to Hardware; 7.4 Summary; References; Chapter 8. Programming Streaming FPGA Applications Using Block Diagrams in Simulink; 8.1 Designing High-Performance Datapaths Using Stream-Based Operators; 8.2 An Image-Processing Design Driver 8.3 Specifying Control in Simulink8.4 Component Reuse: Libraries of Simple and Complex Subsystems; 8.5 Summary; References; Chapter 9. Stream Computations Organized for Reconfigurable Execution; 9.1 Programming; 9.2 System Architecture and Execution Patterns; 9.3 Compilation; 9.4 Runtime; 9.5 Highlights; References; Chapter 10. Programming Data Parallel FPGA Applications Using the SIMD/Vector Model; 10.1 SIMD Computing on FPGAs: An Example; 10.2 SIMD Processing Architectures; 10.3 Data Parallel Languages; 10.4 Reconfigurable Computers for SIMD/Vector Processing 10.5 Variations of SIMD/Vector Computing10.6 Pipelined SIMD/Vector Processing; 10.7 Summary; References; Chapter 11. Operating System Support for Reconfigurable Computing; 11.1 History; 11.2 Abstracted Hardware Resources; 11.3 Flexible Binding; 11.4 Scheduling; 11.5 Communication; 11.6 Synchronization; 11.7 Protection; 11.8 Summary; References; Chapter 12. The JHDL Design and Debug System; 12.1 JHDL Background and Motivation; 12.2 The JHDL Design Language; 12.3 The JHDL CAD System; 12.4 JHDL'S Hardware Mode; 12.5 Advanced JHDL Capabilities; 12.6 Summary; References Part III: Mapping Designs to Reconfigurable Platforms |
| Record Nr. | UNINA-9910818619503321 |
| Amsterdam ; ; Boston, : Morgan Kaufmann, c2008 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Self-organization and autonomic informatics (I) [[electronic resource] /] / edited by H. Czap ... [et al.]
| Self-organization and autonomic informatics (I) [[electronic resource] /] / edited by H. Czap ... [et al.] |
| Pubbl/distr/stampa | Amsterdam ; ; Washington, DC, : IOS Press, c2005 |
| Descrizione fisica | 1 online resource (396 p.) |
| Disciplina | 004 |
| Altri autori (Persone) | CzapHans |
| Collana | Frontiers in artificial intelligence and applications |
| Soggetto topico |
Adaptive computing systems
Artificial intelligence Autonomic computing Computational grids (Computer systems) Self-organizing systems |
| Soggetto genere / forma | Electronic books. |
| ISBN |
6610505160
1-280-50516-8 9786610505166 1-4237-9927-5 1-60750-153-8 600-00-0553-9 1-60129-133-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Title page; Preface; Technical Reviewers; Contents; Self-Organization and Adaptation in General; Self-Organization/Adaptation of Multi-Agent Systems; Self-Organization/Adaptation for Grid Computing; Autonomic Computing in General; Autonomic Communications; Author Index |
| Record Nr. | UNINA-9910451051103321 |
| Amsterdam ; ; Washington, DC, : IOS Press, c2005 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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