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Applied reconfigurable computing : architectures, tools, and applications : 18th international symposium, ARC 2022, virtual event, September 19-20, 2022, proceedings / / Lin Gan [and three others], editors
Applied reconfigurable computing : architectures, tools, and applications : 18th international symposium, ARC 2022, virtual event, September 19-20, 2022, proceedings / / Lin Gan [and three others], editors
Pubbl/distr/stampa Cham, Switzerland : , : Springer, , [2022]
Descrizione fisica 1 online resource (207 pages)
Disciplina 004
Collana Lecture notes in computer science
Soggetto topico Adaptive computing systems
ISBN 3-031-19983-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- 100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs -- 1 Introduction -- 1.1 Related Work -- 2 Background -- 3 Soft Scan-Chain Methodology -- 4 Experimental Results -- References -- FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations -- 1 Introduction -- 2 Background -- 2.1 Classical MD with Tersoff Potential -- 2.2 Prior MD Work -- 3 Efficient Data Transfer -- 3.1 Bandwidth-Friendly Particle Mapping -- 3.2 Zigzagging Buffer Design -- 4 Fixed-Point Design -- 4.1 Dynamic Range Analysis -- 4.2 Precision Analysis -- 5 Custom Dataflow Design -- 6 Evaluation -- 6.1 Environment Setup -- 6.2 Evaluation Performance -- 6.3 Resource Usage Evaluation -- 6.4 Energy Evaluation -- 7 Conclusion -- References -- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA -- 1 Introduction -- 2 CNN-MLPA Architecture -- 2.1 Processing Element -- 2.2 Scheduler -- 2.3 Controller -- 2.4 Configuration Registers -- 3 Evaluation and Results for MLP Operations -- 3.1 Test Platform -- 3.2 CNN-MLPA Configurations -- 3.3 Test Applications -- 3.4 Performance Evaluation of MLP Accelerator -- 3.5 Resource Utilization and Performance Comparison with Other Works -- 4 Accelerator with CNN Feature -- 4.1 Results for Full CNN-MLP Acceleration -- 5 Conclusion -- References -- A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution -- 1 Introduction -- 2 Related Work -- 3 Background Technologies -- 3.1 OpenAI Gym -- 3.2 Versatile Tensor Accelerator -- 3.3 Pyro Library -- 4 Neuroevolutionary Framework Overview -- 4.1 Evolutionary Algorithm Overview -- 4.2 Distribution of Evolutionary Processes -- 5 Detailed SW/HW Architecture of the Neuroevolutionary Agents -- 5.1 Software Subsystem.
5.2 Hardware Subsystem -- 6 Experimental Results -- 6.1 Fitness Evaluation -- 6.2 Architecture Evaluation -- 7 Conclusions and Future Work -- References -- Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation -- 1 Introduction -- 2 Typical Works in Early Stage -- 2.1 Optimization Schemes for SW26010 -- 2.2 Typical Applications -- 3 Recently Development Progress -- 3.1 Optimization Works for SW26010Pro -- 3.2 Pre-processing Functions Within SWLBM -- 3.3 Immersed Boundary Conditions -- 3.4 Other Expert Applications with SWLBM -- 4 Conclusions -- References -- Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network -- 1 Introduction -- 2 Background and Related Work -- 3 Early-Exit Topology and Training -- 4 FPGA Optimization and Deployment -- 5 Evaluation -- 5.1 Entropy Threshold Evaluation -- 5.2 Camera Input Evaluation -- 5.3 Performance and Accuracy Evaluation -- 6 Conclusions and Future Work -- References -- FPGA-Extended General Purpose Computer Architecture -- 1 Introduction -- 2 Challenges -- 3 Solution -- 4 Evaluation -- 4.1 Benchmark Classification -- 4.2 Single-Program -- 4.3 Multi-program -- 5 Feasibility -- 5.1 Reconfiguration Latency Representativeness -- 5.2 Bitstream Cache Dimensions -- 6 Related Work -- 7 Conclusions -- References -- Multi-spectral In-Vivo FPGA-Based Surgical Imaging -- 1 Introduction -- 2 Intelligent Surgical System -- 3 Extraction of Tissue Features -- 3.1 Image Acquisition -- 3.2 CLAHE -- 3.3 Convolution with Derivatives of Gaussian Kernel -- 3.4 Constructing the Hessian Matrix -- 3.5 Eigenvalues of Hessian Matrix -- 3.6 Feature Extraction or ROI Function -- 4 FPGA-Based Image Processing System Architecture -- 4.1 Experimental Setup -- 5 Evaluation -- 5.1 Baseline Design -- 5.2 Convolution Optimisations -- 5.3 Combined Designs.
5.4 Implementation Comparison -- 6 Conclusions -- References -- Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices -- 1 Introduction -- 2 Background -- 2.1 Neural Networks -- 2.2 Deep Learning on Edge Devices -- 2.3 Parallelization Optimizations Using HLS -- 3 Approach -- 3.1 Design Flow -- 3.2 Optimization Algorithm -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Performance Mode -- 4.3 Compact Mode -- 4.4 Comparison Between Performance and Compact Modes -- 4.5 Comparison with State-of-the-Art -- 4.6 Further Work -- 5 Conclusion -- References -- IPEC: Open-Source Design Automation for Inter-Processing Element Communication -- 1 Introduction -- 2 Fundamentals and Terminology -- 3 Related Work -- 4 Capabilities -- 4.1 Connections -- 4.2 Memory -- 4.3 Dispatch - Starting PEs -- 5 Using IPEC to Simplify SoC Implementation -- 5.1 Device, PEs and Memory -- 5.2 Connections -- 5.3 Locks - Deadlock Avoidance -- 5.4 IPEC Intermediate Representation -- 5.5 Interconnect Generation -- 5.6 Address Map Generation -- 5.7 Advantages of Embedding IPEC in Python -- 6 Evaluation -- 6.1 Case Study I: neoDB Database System -- 6.2 Case Study II: Hardware Fuzzing Accelerator -- 7 Conclusion and Future Work -- References -- Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation -- 1 Introduction -- 2 Background -- 2.1 Data Augmentation -- 2.2 Permutation Generation Network -- 3 Accelerator Architecture -- 3.1 Network Structure -- 3.2 Permutation Selection -- 3.3 Further Optimization -- 4 Evaluation -- 4.1 Effect of Using Different Permutations -- 4.2 Comparison to Existing Data Augmentation Methods -- 4.3 Comparison to Existing Permutation Architectures -- 5 Applications -- 5.1 Inference -- 5.2 Training -- 6 Conclusion -- References.
Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features -- 1 Introduction -- 2 Object Tracking with Correlation Filters -- 2.1 MOSSE -- 2.2 KCF -- 2.3 DSST -- 2.4 Convolutional Features -- 3 Previous Work -- 4 The Proposed CF Implementation -- 4.1 CNN Quantisation Using Knowledge Transfer -- 4.2 Software Model Evaluation on VOT2015 -- 4.3 Multichannel MOSSE Filter Implementation on FPGA -- 5 Conclusion -- References -- VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms -- 1 Introduction -- 2 Related Work -- 3 VenOS Framework -- 3.1 VenOS Architecture -- 3.2 Memory Node -- 3.3 User Node -- 3.4 Resource Manager -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Resource Overhead -- 4.3 Virtualization Overhead -- 4.4 Performance Scalability of VenOS Architecture -- 4.5 Interference Among Collocated Accelerators -- 5 Conclusions -- References -- Author Index.
Record Nr. UNINA-9910624397403321
Cham, Switzerland : , : Springer, , [2022]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Applied reconfigurable computing : architectures, tools, and applications : 18th international symposium, ARC 2022, virtual event, September 19-20, 2022, proceedings / / Lin Gan [and three others], editors
Applied reconfigurable computing : architectures, tools, and applications : 18th international symposium, ARC 2022, virtual event, September 19-20, 2022, proceedings / / Lin Gan [and three others], editors
Pubbl/distr/stampa Cham, Switzerland : , : Springer, , [2022]
Descrizione fisica 1 online resource (207 pages)
Disciplina 004
Collana Lecture notes in computer science
Soggetto topico Adaptive computing systems
ISBN 3-031-19983-9
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- 100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs -- 1 Introduction -- 1.1 Related Work -- 2 Background -- 3 Soft Scan-Chain Methodology -- 4 Experimental Results -- References -- FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations -- 1 Introduction -- 2 Background -- 2.1 Classical MD with Tersoff Potential -- 2.2 Prior MD Work -- 3 Efficient Data Transfer -- 3.1 Bandwidth-Friendly Particle Mapping -- 3.2 Zigzagging Buffer Design -- 4 Fixed-Point Design -- 4.1 Dynamic Range Analysis -- 4.2 Precision Analysis -- 5 Custom Dataflow Design -- 6 Evaluation -- 6.1 Environment Setup -- 6.2 Evaluation Performance -- 6.3 Resource Usage Evaluation -- 6.4 Energy Evaluation -- 7 Conclusion -- References -- A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA -- 1 Introduction -- 2 CNN-MLPA Architecture -- 2.1 Processing Element -- 2.2 Scheduler -- 2.3 Controller -- 2.4 Configuration Registers -- 3 Evaluation and Results for MLP Operations -- 3.1 Test Platform -- 3.2 CNN-MLPA Configurations -- 3.3 Test Applications -- 3.4 Performance Evaluation of MLP Accelerator -- 3.5 Resource Utilization and Performance Comparison with Other Works -- 4 Accelerator with CNN Feature -- 4.1 Results for Full CNN-MLP Acceleration -- 5 Conclusion -- References -- A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution -- 1 Introduction -- 2 Related Work -- 3 Background Technologies -- 3.1 OpenAI Gym -- 3.2 Versatile Tensor Accelerator -- 3.3 Pyro Library -- 4 Neuroevolutionary Framework Overview -- 4.1 Evolutionary Algorithm Overview -- 4.2 Distribution of Evolutionary Processes -- 5 Detailed SW/HW Architecture of the Neuroevolutionary Agents -- 5.1 Software Subsystem.
5.2 Hardware Subsystem -- 6 Experimental Results -- 6.1 Fitness Evaluation -- 6.2 Architecture Evaluation -- 7 Conclusions and Future Work -- References -- Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation -- 1 Introduction -- 2 Typical Works in Early Stage -- 2.1 Optimization Schemes for SW26010 -- 2.2 Typical Applications -- 3 Recently Development Progress -- 3.1 Optimization Works for SW26010Pro -- 3.2 Pre-processing Functions Within SWLBM -- 3.3 Immersed Boundary Conditions -- 3.4 Other Expert Applications with SWLBM -- 4 Conclusions -- References -- Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network -- 1 Introduction -- 2 Background and Related Work -- 3 Early-Exit Topology and Training -- 4 FPGA Optimization and Deployment -- 5 Evaluation -- 5.1 Entropy Threshold Evaluation -- 5.2 Camera Input Evaluation -- 5.3 Performance and Accuracy Evaluation -- 6 Conclusions and Future Work -- References -- FPGA-Extended General Purpose Computer Architecture -- 1 Introduction -- 2 Challenges -- 3 Solution -- 4 Evaluation -- 4.1 Benchmark Classification -- 4.2 Single-Program -- 4.3 Multi-program -- 5 Feasibility -- 5.1 Reconfiguration Latency Representativeness -- 5.2 Bitstream Cache Dimensions -- 6 Related Work -- 7 Conclusions -- References -- Multi-spectral In-Vivo FPGA-Based Surgical Imaging -- 1 Introduction -- 2 Intelligent Surgical System -- 3 Extraction of Tissue Features -- 3.1 Image Acquisition -- 3.2 CLAHE -- 3.3 Convolution with Derivatives of Gaussian Kernel -- 3.4 Constructing the Hessian Matrix -- 3.5 Eigenvalues of Hessian Matrix -- 3.6 Feature Extraction or ROI Function -- 4 FPGA-Based Image Processing System Architecture -- 4.1 Experimental Setup -- 5 Evaluation -- 5.1 Baseline Design -- 5.2 Convolution Optimisations -- 5.3 Combined Designs.
5.4 Implementation Comparison -- 6 Conclusions -- References -- Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices -- 1 Introduction -- 2 Background -- 2.1 Neural Networks -- 2.2 Deep Learning on Edge Devices -- 2.3 Parallelization Optimizations Using HLS -- 3 Approach -- 3.1 Design Flow -- 3.2 Optimization Algorithm -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Performance Mode -- 4.3 Compact Mode -- 4.4 Comparison Between Performance and Compact Modes -- 4.5 Comparison with State-of-the-Art -- 4.6 Further Work -- 5 Conclusion -- References -- IPEC: Open-Source Design Automation for Inter-Processing Element Communication -- 1 Introduction -- 2 Fundamentals and Terminology -- 3 Related Work -- 4 Capabilities -- 4.1 Connections -- 4.2 Memory -- 4.3 Dispatch - Starting PEs -- 5 Using IPEC to Simplify SoC Implementation -- 5.1 Device, PEs and Memory -- 5.2 Connections -- 5.3 Locks - Deadlock Avoidance -- 5.4 IPEC Intermediate Representation -- 5.5 Interconnect Generation -- 5.6 Address Map Generation -- 5.7 Advantages of Embedding IPEC in Python -- 6 Evaluation -- 6.1 Case Study I: neoDB Database System -- 6.2 Case Study II: Hardware Fuzzing Accelerator -- 7 Conclusion and Future Work -- References -- Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation -- 1 Introduction -- 2 Background -- 2.1 Data Augmentation -- 2.2 Permutation Generation Network -- 3 Accelerator Architecture -- 3.1 Network Structure -- 3.2 Permutation Selection -- 3.3 Further Optimization -- 4 Evaluation -- 4.1 Effect of Using Different Permutations -- 4.2 Comparison to Existing Data Augmentation Methods -- 4.3 Comparison to Existing Permutation Architectures -- 5 Applications -- 5.1 Inference -- 5.2 Training -- 6 Conclusion -- References.
Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features -- 1 Introduction -- 2 Object Tracking with Correlation Filters -- 2.1 MOSSE -- 2.2 KCF -- 2.3 DSST -- 2.4 Convolutional Features -- 3 Previous Work -- 4 The Proposed CF Implementation -- 4.1 CNN Quantisation Using Knowledge Transfer -- 4.2 Software Model Evaluation on VOT2015 -- 4.3 Multichannel MOSSE Filter Implementation on FPGA -- 5 Conclusion -- References -- VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms -- 1 Introduction -- 2 Related Work -- 3 VenOS Framework -- 3.1 VenOS Architecture -- 3.2 Memory Node -- 3.3 User Node -- 3.4 Resource Manager -- 4 Evaluation -- 4.1 Experimental Setup -- 4.2 Resource Overhead -- 4.3 Virtualization Overhead -- 4.4 Performance Scalability of VenOS Architecture -- 4.5 Interference Among Collocated Accelerators -- 5 Conclusions -- References -- Author Index.
Record Nr. UNISA-996495566203316
Cham, Switzerland : , : Springer, , [2022]
Materiale a stampa
Lo trovi qui: Univ. di Salerno
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications : 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings / / Francesca Palumbo [and three others], editors
Applied Reconfigurable Computing. Architectures, Tools, and Applications : 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings / / Francesca Palumbo [and three others], editors
Edizione [First edition.]
Pubbl/distr/stampa Cham, Switzerland : , : Springer Nature Switzerland AG, , [2023]
Descrizione fisica 1 online resource (380 pages)
Disciplina 004
Collana Lecture Notes in Computer Science Series
Soggetto topico Adaptive computing systems
ISBN 3-031-42921-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- Design Methods and Tools -- High-Level Synthesis of Memory Systems for Decoupled Data Orchestration -- 1 Introduction -- 2 Background and Related Work -- 2.1 Taxonomy of Data Orchestration -- 2.2 Storage Idioms -- 3 PIPO: An Data Structure for Decoupled Data Orchestration -- 3.1 Definition of PIPO -- 3.2 Automatic Insertion of API Calls -- 4 Automatic Decoupling of Data Orchestration -- 4.1 RAM-Wise Decoupling -- 4.2 Decoupling Algorithm -- 4.3 Compilation Example -- 5 Automatic Partial Decoupling -- 5.1 Partial Decoupling Based on the Fork-Join Model -- 5.2 Automatically Determining the Fork and Join Points -- 6 BuffetLike: Another Data Structure for Decoupled Data Orchestration -- 7 Evaluation -- 7.1 Experimental Setup -- 7.2 Execution Time -- 7.3 Resource Utilization -- 7.4 Discussion -- 8 Conclusion -- References -- Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis -- 1 Introduction -- 2 Background and Motivation -- 2.1 Different Micro-architecture Design Tools -- 2.2 HLS Limitation in Pipelining an Instruction Set Simulator -- 3 Related Work -- 3.1 Deploying Speculative and Dynamic Techniques in HLS -- 3.2 Pipelined CPU Designs Using HLS -- 3.3 Dynamic Hart Scheduling in Multi-threaded CPU and GPU -- 4 Proposed Approach -- 4.1 Static Multi-threaded RISC-V Core -- 4.2 Dynamic Single-Threaded RISC-V Core -- 4.3 Dynamic Multi-threaded RISC-V Core -- 4.4 Thread Synchronization -- 4.5 Shared-Memory RISC-V Multi-core -- 5 Experimental Validation -- 6 Conclusion -- References -- NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs -- 1 Introduction -- 2 Storage Technologies and Related Work -- 2.1 NVM Storage Technologies -- 2.2 Related Work -- 3 Proposed Approach -- 3.1 NVMulator Micro-Architecture -- 3.2 TaPaSCo Integration.
4 Experimental Setup and Evaluation -- 4.1 Latency -- 4.2 FIO Bandwidth -- 4.3 Database Application -- 5 Conclusion -- References -- On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs -- 1 Introduction -- 2 Related Work -- 3 Methodology -- 3.1 Application Software -- 3.2 Custom Device Driver and Kernel Interaction -- 4 CNN Application -- 5 Results and Discussion -- 6 Conclusion and Future Work -- References -- Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE -- 1 Introduction -- 2 Background -- 2.1 Related Work -- 2.2 Posit Numbers -- 2.3 Principle of Circuit Simulation with SPICE -- 3 Analysis of Number Formats in SPICE -- 3.1 Distribution of Operations -- 3.2 Impact on Convergence and Output Error -- 3.3 Impact on Simulation Runtime -- 4 Operator Implementation -- 5 Whole Application Analysis -- 6 Conclusion -- References -- Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System -- 1 Introduction -- 2 Background and Related Work -- 2.1 DRAM Performance -- 2.2 Related Work -- 3 The Proposed Approach -- 3.1 Task's Memory Characteristics -- 3.2 Memory Model-Aware (MMA) Scheduling -- 3.3 Memory Access Pattern-Aware (MAPA) Scheduling -- 4 Evaluation -- 4.1 Evaluation Design -- 4.2 Results and Discussion -- 5 Conclusion -- References -- ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures -- 1 Introduction -- 2 Related Work -- 3 Framework -- 3.1 Library Module -- 3.2 Graph Creation Module -- 3.3 Hardware Creation Module -- 4 Evaluation -- 5 Conclusion -- References -- Applications -- FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing -- 1 Introduction -- 2 Related Work -- 3 Architecture and Optimizations -- 3.1 Bag of Little Bootstraps for AQP -- 3.2 Streaming BLB.
3.3 Gauss Random Number Generator (GRNG) -- 3.4 BLB Block Design -- 4 Test Setup for Evaluation -- 4.1 Hardware Platform -- 4.2 Test System Structure -- 4.3 CPU Implementation -- 5 Evaluation -- 6 Conclusion -- References -- Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows -- 1 Introduction -- 2 Related Work and Motivation -- 3 Dataflow Description -- 3.1 Combination Engine -- 3.2 Aggregation Engine -- 4 Dataflow Optimization -- 5 Multi-threaded Extension -- 6 Pytorch Integration -- 7 Performance Evaluation -- 8 Conclusions -- References -- DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator -- 1 Introduction -- 2 Background -- 2.1 Versatile Tensor Accelerator -- 2.2 Reverse Engineering DNN Architecture -- 2.3 Threat Model -- 3 Methodology -- 3.1 Hardware Trojan Design -- 3.2 Predicting the Layer Hyperparameters -- 4 Experiment Results -- 4.1 Demonstration of Our Attack on ResNet18 -- 4.2 Evaluation of Our Attack on Randomly-chained DNNs -- 4.3 Hardware Trojan Overheads -- 5 Limitations and Future Work -- 6 Conclusion -- References -- Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations -- 1 Introduction -- 2 SNOW 3G and SNOW-V -- 2.1 The SNOW 3G Algorithm -- 2.2 The SNOW-V Algorithm -- 3 Proposed Multi-mode Architectures -- 3.1 SNOW-3G/V for Area Efficiency -- 3.2 SNOW-3G/V for High Performance -- 4 Experimental Results and Comparisons -- 5 Conclusions -- References -- A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment*-1pc -- 1 Introduction -- 2 State of the Art -- 3 Concept of a Displaced Vertex Trigger -- 3.1 Hit Image Converter -- 3.2 Parallel Convolution Layer -- 3.3 Training -- 3.4 Hardware Generator -- 4 Result -- 5 Summary -- References.
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding -- 1 Introduction -- 2 Related Works -- 3 Methods -- 3.1 Neural Recording and Decoding Problem -- 3.2 Signal Processing: Spike Detection -- 3.3 Neural Decoding -- 3.4 Training Scheme -- 4 Hardware Architecture -- 4.1 PC-FPGA Communication -- 4.2 Spiking Neural Network Architecture -- 5 Discussion -- 5.1 Accuracy -- 5.2 Resource Utilization -- 5.3 Power Consumption -- 5.4 Adaptability to Different Experiments -- 6 Comparison with State of Art -- 7 Conclusion -- References -- Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA -- 1 Introduction -- 2 Previous Work -- 3 Implementation of the Perception and Control System -- 3.1 Detection-Segmentation Network in SoC FPGA -- 3.2 Vehicle Control Algorithm -- 3.3 Hardware Setup -- 4 Evaluation of the Detection-Segmentation Network -- 5 Conclusion -- References -- Architectures -- Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC*-1pc -- 1 Introduction -- 2 Related Work -- 3 Development of Fault-Tolerance Techniques -- 3.1 HW/SW Fault-Tolerant Architecture -- 3.2 Coarse-Grained Application-Independent Redundancy -- 3.3 Fine-Grained Application-Specific Redundancy -- 3.4 Correction of Configuration Memory -- 4 Experimental Evaluation -- 4.1 Fault Injection and Evaluation Campaign -- 4.2 Experimental Results -- 5 Conclusion -- References -- Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture -- 1 Introduction -- 2 Background: ReRAM for In-Memory NN Computing -- 3 Related Work -- 4 Proposed Architecture -- 4.1 Overall Architecture -- 4.2 GPU Layer -- 4.3 ReRAM Layer -- 4.4 Offloading: Selecting the Best Layers for ReRAM Acceleration -- 5 Evaluation Methodology -- 6 Results -- 6.1 Synthesis Results.
6.2 Computing Efficiency -- 6.3 Inference Accuracy -- 6.4 Energy Consumption -- 7 Conclusion and Future Work -- References -- On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64 -- 1 Introduction -- 2 Related Work -- 2.1 Real-Time Scheduling and Shared Resources on FPGAs -- 2.2 Operating Systems for FPGAs -- 2.3 Fixed-Priority Multi-processor Scheduling -- 3 System Architecture -- 4 Task Model and Runtime System -- 4.1 Task Model -- 4.2 Runtime System -- 5 Schedulability Analysis -- 6 Practical Example -- 6.1 Implementation Based on ReconOS64 -- 6.2 Exemplary Task Set -- 6.3 Applying the Schedulability Test -- 7 Conclusion and Future Work -- References -- Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning*-1pc -- 1 Introduction -- 2 Learning Techniques for SNNs -- 3 The Proposed SNN-Based SoC Architecture -- 4 Proposed Learning Strategy -- 5 Data Encoding Strategy -- 6 Evaluation Setup -- 6.1 Iris Problem -- 6.2 Breast Cancer Wisconsin Dataset -- 6.3 Pima Indian Diabetes Dataset -- 6.4 Wine Dataset -- 6.5 The Mountain Car Environment -- 7 Experimental Results -- 7.1 Resource Utilization -- 7.2 Accuracy Results -- 8 Conclusions and Future Work -- References -- More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding -- 1 Introduction -- 2 Related Work -- 3 Computation Coding on FPGAs -- 3.1 Decomposition Algorithm -- 3.2 Hardware Designs -- 4 Hardware Generation Using Primitive Instantiation -- 4.1 Python Hardware Interface -- 4.2 TIAs on FPGAs -- 4.3 Primitive Generation -- 5 Evaluation -- 5.1 Setup -- 5.2 Comparison Between CMM Designs and SoA -- 6 Conclusion -- References -- Energy Efficient DNN Compaction for Edge Deployment -- 1 Introduction -- 2 Related Works -- 3 Proposed Approach -- 4 Experiments and Results -- 4.1 Experimental Setup -- 4.2 Results and Discussion.
5 Conclusion.
Record Nr. UNINA-9910746070903321
Cham, Switzerland : , : Springer Nature Switzerland AG, , [2023]
Materiale a stampa
Lo trovi qui: Univ. Federico II
Opac: Controlla la disponibilità qui
Applied Reconfigurable Computing. Architectures, Tools, and Applications : 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings / / Francesca Palumbo [and three others], editors
Applied Reconfigurable Computing. Architectures, Tools, and Applications : 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings / / Francesca Palumbo [and three others], editors
Edizione [First edition.]
Pubbl/distr/stampa Cham, Switzerland : , : Springer Nature Switzerland AG, , [2023]
Descrizione fisica 1 online resource (380 pages)
Disciplina 004
Collana Lecture Notes in Computer Science Series
Soggetto topico Adaptive computing systems
ISBN 3-031-42921-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- Design Methods and Tools -- High-Level Synthesis of Memory Systems for Decoupled Data Orchestration -- 1 Introduction -- 2 Background and Related Work -- 2.1 Taxonomy of Data Orchestration -- 2.2 Storage Idioms -- 3 PIPO: An Data Structure for Decoupled Data Orchestration -- 3.1 Definition of PIPO -- 3.2 Automatic Insertion of API Calls -- 4 Automatic Decoupling of Data Orchestration -- 4.1 RAM-Wise Decoupling -- 4.2 Decoupling Algorithm -- 4.3 Compilation Example -- 5 Automatic Partial Decoupling -- 5.1 Partial Decoupling Based on the Fork-Join Model -- 5.2 Automatically Determining the Fork and Join Points -- 6 BuffetLike: Another Data Structure for Decoupled Data Orchestration -- 7 Evaluation -- 7.1 Experimental Setup -- 7.2 Execution Time -- 7.3 Resource Utilization -- 7.4 Discussion -- 8 Conclusion -- References -- Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis -- 1 Introduction -- 2 Background and Motivation -- 2.1 Different Micro-architecture Design Tools -- 2.2 HLS Limitation in Pipelining an Instruction Set Simulator -- 3 Related Work -- 3.1 Deploying Speculative and Dynamic Techniques in HLS -- 3.2 Pipelined CPU Designs Using HLS -- 3.3 Dynamic Hart Scheduling in Multi-threaded CPU and GPU -- 4 Proposed Approach -- 4.1 Static Multi-threaded RISC-V Core -- 4.2 Dynamic Single-Threaded RISC-V Core -- 4.3 Dynamic Multi-threaded RISC-V Core -- 4.4 Thread Synchronization -- 4.5 Shared-Memory RISC-V Multi-core -- 5 Experimental Validation -- 6 Conclusion -- References -- NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs -- 1 Introduction -- 2 Storage Technologies and Related Work -- 2.1 NVM Storage Technologies -- 2.2 Related Work -- 3 Proposed Approach -- 3.1 NVMulator Micro-Architecture -- 3.2 TaPaSCo Integration.
4 Experimental Setup and Evaluation -- 4.1 Latency -- 4.2 FIO Bandwidth -- 4.3 Database Application -- 5 Conclusion -- References -- On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs -- 1 Introduction -- 2 Related Work -- 3 Methodology -- 3.1 Application Software -- 3.2 Custom Device Driver and Kernel Interaction -- 4 CNN Application -- 5 Results and Discussion -- 6 Conclusion and Future Work -- References -- Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE -- 1 Introduction -- 2 Background -- 2.1 Related Work -- 2.2 Posit Numbers -- 2.3 Principle of Circuit Simulation with SPICE -- 3 Analysis of Number Formats in SPICE -- 3.1 Distribution of Operations -- 3.2 Impact on Convergence and Output Error -- 3.3 Impact on Simulation Runtime -- 4 Operator Implementation -- 5 Whole Application Analysis -- 6 Conclusion -- References -- Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System -- 1 Introduction -- 2 Background and Related Work -- 2.1 DRAM Performance -- 2.2 Related Work -- 3 The Proposed Approach -- 3.1 Task's Memory Characteristics -- 3.2 Memory Model-Aware (MMA) Scheduling -- 3.3 Memory Access Pattern-Aware (MAPA) Scheduling -- 4 Evaluation -- 4.1 Evaluation Design -- 4.2 Results and Discussion -- 5 Conclusion -- References -- ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures -- 1 Introduction -- 2 Related Work -- 3 Framework -- 3.1 Library Module -- 3.2 Graph Creation Module -- 3.3 Hardware Creation Module -- 4 Evaluation -- 5 Conclusion -- References -- Applications -- FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing -- 1 Introduction -- 2 Related Work -- 3 Architecture and Optimizations -- 3.1 Bag of Little Bootstraps for AQP -- 3.2 Streaming BLB.
3.3 Gauss Random Number Generator (GRNG) -- 3.4 BLB Block Design -- 4 Test Setup for Evaluation -- 4.1 Hardware Platform -- 4.2 Test System Structure -- 4.3 CPU Implementation -- 5 Evaluation -- 6 Conclusion -- References -- Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows -- 1 Introduction -- 2 Related Work and Motivation -- 3 Dataflow Description -- 3.1 Combination Engine -- 3.2 Aggregation Engine -- 4 Dataflow Optimization -- 5 Multi-threaded Extension -- 6 Pytorch Integration -- 7 Performance Evaluation -- 8 Conclusions -- References -- DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator -- 1 Introduction -- 2 Background -- 2.1 Versatile Tensor Accelerator -- 2.2 Reverse Engineering DNN Architecture -- 2.3 Threat Model -- 3 Methodology -- 3.1 Hardware Trojan Design -- 3.2 Predicting the Layer Hyperparameters -- 4 Experiment Results -- 4.1 Demonstration of Our Attack on ResNet18 -- 4.2 Evaluation of Our Attack on Randomly-chained DNNs -- 4.3 Hardware Trojan Overheads -- 5 Limitations and Future Work -- 6 Conclusion -- References -- Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations -- 1 Introduction -- 2 SNOW 3G and SNOW-V -- 2.1 The SNOW 3G Algorithm -- 2.2 The SNOW-V Algorithm -- 3 Proposed Multi-mode Architectures -- 3.1 SNOW-3G/V for Area Efficiency -- 3.2 SNOW-3G/V for High Performance -- 4 Experimental Results and Comparisons -- 5 Conclusions -- References -- A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment*-1pc -- 1 Introduction -- 2 State of the Art -- 3 Concept of a Displaced Vertex Trigger -- 3.1 Hit Image Converter -- 3.2 Parallel Convolution Layer -- 3.3 Training -- 3.4 Hardware Generator -- 4 Result -- 5 Summary -- References.
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding -- 1 Introduction -- 2 Related Works -- 3 Methods -- 3.1 Neural Recording and Decoding Problem -- 3.2 Signal Processing: Spike Detection -- 3.3 Neural Decoding -- 3.4 Training Scheme -- 4 Hardware Architecture -- 4.1 PC-FPGA Communication -- 4.2 Spiking Neural Network Architecture -- 5 Discussion -- 5.1 Accuracy -- 5.2 Resource Utilization -- 5.3 Power Consumption -- 5.4 Adaptability to Different Experiments -- 6 Comparison with State of Art -- 7 Conclusion -- References -- Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA -- 1 Introduction -- 2 Previous Work -- 3 Implementation of the Perception and Control System -- 3.1 Detection-Segmentation Network in SoC FPGA -- 3.2 Vehicle Control Algorithm -- 3.3 Hardware Setup -- 4 Evaluation of the Detection-Segmentation Network -- 5 Conclusion -- References -- Architectures -- Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC*-1pc -- 1 Introduction -- 2 Related Work -- 3 Development of Fault-Tolerance Techniques -- 3.1 HW/SW Fault-Tolerant Architecture -- 3.2 Coarse-Grained Application-Independent Redundancy -- 3.3 Fine-Grained Application-Specific Redundancy -- 3.4 Correction of Configuration Memory -- 4 Experimental Evaluation -- 4.1 Fault Injection and Evaluation Campaign -- 4.2 Experimental Results -- 5 Conclusion -- References -- Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture -- 1 Introduction -- 2 Background: ReRAM for In-Memory NN Computing -- 3 Related Work -- 4 Proposed Architecture -- 4.1 Overall Architecture -- 4.2 GPU Layer -- 4.3 ReRAM Layer -- 4.4 Offloading: Selecting the Best Layers for ReRAM Acceleration -- 5 Evaluation Methodology -- 6 Results -- 6.1 Synthesis Results.
6.2 Computing Efficiency -- 6.3 Inference Accuracy -- 6.4 Energy Consumption -- 7 Conclusion and Future Work -- References -- On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64 -- 1 Introduction -- 2 Related Work -- 2.1 Real-Time Scheduling and Shared Resources on FPGAs -- 2.2 Operating Systems for FPGAs -- 2.3 Fixed-Priority Multi-processor Scheduling -- 3 System Architecture -- 4 Task Model and Runtime System -- 4.1 Task Model -- 4.2 Runtime System -- 5 Schedulability Analysis -- 6 Practical Example -- 6.1 Implementation Based on ReconOS64 -- 6.2 Exemplary Task Set -- 6.3 Applying the Schedulability Test -- 7 Conclusion and Future Work -- References -- Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning*-1pc -- 1 Introduction -- 2 Learning Techniques for SNNs -- 3 The Proposed SNN-Based SoC Architecture -- 4 Proposed Learning Strategy -- 5 Data Encoding Strategy -- 6 Evaluation Setup -- 6.1 Iris Problem -- 6.2 Breast Cancer Wisconsin Dataset -- 6.3 Pima Indian Diabetes Dataset -- 6.4 Wine Dataset -- 6.5 The Mountain Car Environment -- 7 Experimental Results -- 7.1 Resource Utilization -- 7.2 Accuracy Results -- 8 Conclusions and Future Work -- References -- More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding -- 1 Introduction -- 2 Related Work -- 3 Computation Coding on FPGAs -- 3.1 Decomposition Algorithm -- 3.2 Hardware Designs -- 4 Hardware Generation Using Primitive Instantiation -- 4.1 Python Hardware Interface -- 4.2 TIAs on FPGAs -- 4.3 Primitive Generation -- 5 Evaluation -- 5.1 Setup -- 5.2 Comparison Between CMM Designs and SoA -- 6 Conclusion -- References -- Energy Efficient DNN Compaction for Edge Deployment -- 1 Introduction -- 2 Related Works -- 3 Proposed Approach -- 4 Experiments and Results -- 4.1 Experimental Setup -- 4.2 Results and Discussion.
5 Conclusion.
Record Nr. UNISA-996550556703316
Cham, Switzerland : , : Springer Nature Switzerland AG, , [2023]
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ARM 2015 : proceedings of the 14th Workshop on Adaptive and Reflective Middleware : collocated with ACM/IFIP/USENIX Middleware 2015 : December 8, 2015, Vancouver, Canada / / workshop co-chairs, Nikolaos Georgantas and Aniruddha Gokhale
ARM 2015 : proceedings of the 14th Workshop on Adaptive and Reflective Middleware : collocated with ACM/IFIP/USENIX Middleware 2015 : December 8, 2015, Vancouver, Canada / / workshop co-chairs, Nikolaos Georgantas and Aniruddha Gokhale
Pubbl/distr/stampa New York : , : ACM, , 2015
Descrizione fisica 1 online resource (55 pages)
Disciplina 005.713
Soggetto topico Middleware
Adaptive computing systems
ISBN 1-4503-3733-3
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti Adaptive and Reflective Middleware 2015
Proceedings of the 14th International Workshop on Adaptive and Reflective Middleware
Record Nr. UNINA-9910376542903321
New York : , : ACM, , 2015
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ARM 2016 : the 15th Workshop on Adaptive and Reflective Middleware : colocated with ACM/IFIP/USENIX Middleware 2016, 12th-16th December 2016, Trento, Italy / / sponsors, Association for Computing Machinery, IFIP, USENIX the Advanced Computing System Association
ARM 2016 : the 15th Workshop on Adaptive and Reflective Middleware : colocated with ACM/IFIP/USENIX Middleware 2016, 12th-16th December 2016, Trento, Italy / / sponsors, Association for Computing Machinery, IFIP, USENIX the Advanced Computing System Association
Pubbl/distr/stampa New York : , : ACM, , 2016
Descrizione fisica 1 online resource (40 pages)
Disciplina 005.713
Soggetto topico Middleware
Adaptive computing systems
ISBN 1-4503-4662-6
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti Adaptive and Reflective Middleware 2016
Proceedings of the 15th International Workshop on Adaptive and Reflective Middleware
Record Nr. UNINA-9910376428803321
New York : , : ACM, , 2016
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Blocks, towards energy-efficient, coarse-grained reconfigurable architectures / / Mark Wijtvliet, Henk Corporaal, Akash Kumar
Blocks, towards energy-efficient, coarse-grained reconfigurable architectures / / Mark Wijtvliet, Henk Corporaal, Akash Kumar
Autore Wijtvliet Mark
Edizione [1st ed. 2022.]
Pubbl/distr/stampa Cham, Switzerland : , : Springer, , [2022]
Descrizione fisica 1 online resource (X, 220 p. 158 illus., 117 illus. in color.)
Disciplina 004
Soggetto topico Adaptive computing systems
ISBN 3-030-79774-0
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Introduction -- CGRA background -- Concept of the Blocks architecture -- The Blocks framework -- Energy, area, and performance evaluation -- Architectural model -- Case study: the BrainSense platform -- Conclusion.
Record Nr. UNINA-9910523003403321
Wijtvliet Mark  
Cham, Switzerland : , : Springer, , [2022]
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Complex adaptive systems modeling
Complex adaptive systems modeling
Pubbl/distr/stampa Heidelberg, Germany : , : Springer-Verlag, GmbH, , 2013-
Descrizione fisica 1 online resource
Soggetto topico Adaptive control systems
Adaptive computing systems
Soggetto genere / forma Periodicals.
Soggetto non controllato Mechanical Engineering - General
ISSN 2194-3206
Formato Materiale a stampa
Livello bibliografico Periodico
Lingua di pubblicazione eng
Altri titoli varianti CASM
CAS modeling
Record Nr. UNINA-9910130572203321
Heidelberg, Germany : , : Springer-Verlag, GmbH, , 2013-
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Complex adaptive systems modeling
Complex adaptive systems modeling
Pubbl/distr/stampa Heidelberg, Germany : , : Springer-Verlag, GmbH, , 2013-
Descrizione fisica 1 online resource
Soggetto topico Adaptive control systems
Adaptive computing systems
Soggetto genere / forma Periodicals.
Soggetto non controllato Mechanical Engineering - General
ISSN 2194-3206
Formato Materiale a stampa
Livello bibliografico Periodico
Lingua di pubblicazione eng
Altri titoli varianti CASM
CAS modeling
Record Nr. UNISA-996208498103316
Heidelberg, Germany : , : Springer-Verlag, GmbH, , 2013-
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From animals to animats 16 : 16th international conference on simulation of adaptive behavior, SAB 2022, Cergy-Pontoise, France, September 20-23, 2022 : proceedings / / Lola Cañamero [and four others], editors
From animals to animats 16 : 16th international conference on simulation of adaptive behavior, SAB 2022, Cergy-Pontoise, France, September 20-23, 2022 : proceedings / / Lola Cañamero [and four others], editors
Pubbl/distr/stampa Cham, Switzerland : , : Springer Nature Switzerland AG, , [2022]
Descrizione fisica 1 online resource (225 pages)
Disciplina 004
Collana Lecture Notes in Artificial Intelligence
Soggetto topico Computer vision
Adaptive computing systems
Robotics
ISBN 3-031-16770-8
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- Organization -- Contents -- Embodiment -- How to Design Morphologies. A Design Process for Autonomous Robots -- 1 Introduction -- 2 Proposal of a Design Process -- 2.1 Arc Representation -- 2.2 Morphological Manifold as a Directed Graph -- 2.3 Algorithmically Determined Motion Sequences -- 2.4 Plug'n'Clamp Kit -- 3 Evaluation -- 4 Discussion and Outlook -- References -- Exploring Sensitization in the Context of Extending the Behavior of an Artificial Agent -- 1 Introduction -- 2 Sensitization -- 3 IDSM -- 4 Model of Pseudo-conditioning Through Generalization of Nodes -- 5 Experiments and Results -- 5.1 Setup -- 5.2 Results -- 6 Discussion -- References -- Investigating a Minimal Categorical Perception Task with a Node-Based Sensorimotor Map -- 1 Introduction -- 2 Model -- 2.1 NB-SMM -- 2.2 Experiment Setup -- 2.3 CTRNN Comparison -- 3 Results -- 3.1 NB-SMM Results -- 3.2 Categorical Perception -- 3.3 CTRNN Results -- 4 Discussion -- References -- Deep Gaussian Processes for Angle and Position Discrimination in Active Touch Sensing -- 1 Introduction -- 2 Methods -- 2.1 Dataset -- 2.2 Dimensionality Reduction -- 2.3 Gaussian Process Based Models -- 3 Results -- 3.1 Position Discrimination -- 3.2 Angle Discrimination -- 4 Discussion and Future Work -- References -- Neural Body Bending Control with Temporal Delays for Millipede-Like Turning Behaviour of a Multi-segmented, Legged Robot -- 1 Introduction -- 2 Materials and Methods -- 2.1 Millipede-Inspired Robot -- 2.2 Neural Control System for Millipede-Like Turning Behaviour -- 2.3 Neural Body Bending Control with Temporal Delays -- 3 Experiments and Results -- 3.1 Millipede-Like Turning Behaviour -- 3.2 Navigation in Different Environments with Narrow Paths -- 4 Conclusion -- References -- Brain-Inspired Control, Adaptation, and Learning.
Yoking-Based Identification of Learning Behavior in Artificial and Biological Agents -- 1 Introduction -- 2 Related Work -- 3 Comparing Synthetic Learning Models to Target Data -- 3.1 Problem Formalization -- 3.2 Unconstrained Approach to Identify Learning Algorithms -- 3.3 Yoked Approach to Identify Learning Algorithms -- 4 Evaluation in a Synthetic Lockbox Task -- 4.1 Identifying Known Ground Truth Learning Algorithms -- 4.2 Comparison over Size of Action Space -- 5 Evaluation in a Real Cockatoo Lockbox Learning Task -- 6 Conclusion -- References -- Is Free Energy an Organizational Principle in Spiking Neural Networks? -- 1 Introduction: Decoding the Free Energy Concept -- 2 Free Energy in the Absence of External Sensing -- 3 Non-variational Free Energy in a Spiking Neural Network -- 4 Conclusions -- 5 Supplemental Information -- References -- Create Efficient and Complex Reservoir Computing Architectures with ReservoirPy -- 1 Introduction -- 2 Flexible Reservoir Computing -- 2.1 Functional Nodes -- 2.2 Learning Rules -- 2.3 Models as Computational Graphs -- 2.4 Feedback Loops -- 3 Getting Started: ESN for Timeseries Forecasting with ReservoirPy -- 3.1 Step 1: Choose a Timeseries for One Timestep Ahead Prediction -- 3.2 Step 2: Define Your ESN -- 3.3 Step 3.1: Train the Offline Model -- 3.4 Step 3.2: Train the Online Model -- 3.5 Step 4: Evaluate the Model -- 4 Discussion -- References -- Adaptive Inhibition for Optimal Energy Consumption by Animals, Robots and Neurocomputers -- 1 Introduction -- 1.1 Specific and Non-specific Inhibition in Animals -- 1.2 The Quality of Cognitive Processes -- 2 Energy Measurements in a Physical System -- 3 Adaptive Inhibition -- 4 Discussion -- References -- Adapting to Environment Changes Through Neuromodulation of Reinforcement Learning -- 1 Introduction -- 2 Problem -- 2.1 Reinforcement Learning.
2.2 Environment Changes -- 3 Method -- 3.1 ACh and NE Neuromodulation -- 3.2 Update of ACh and NE System -- 3.3 The Complete System -- 4 Experiments -- 5 Results -- 5.1 Reinforcement Learning Performance -- 5.2 Activity of Neuromodulatory System -- 6 Conclusion -- References -- Multi-task Learning with Modular Reinforcement Learning -- 1 Introduction -- 2 Related Work -- 3 Preliminaries -- 3.1 Reinforcement Learning -- 3.2 Modular Reinforcement Learning -- 4 The Inverse Arbi-Q Architecture -- 5 Implementation -- 5.1 State Predictor -- 5.2 Reward Predictor -- 5.3 RL Controller -- 5.4 Action Selection -- 6 Simulation -- 6.1 Settings -- 6.2 Results -- 7 Conclusions and Future Work -- References -- Bio-inspired Vision and Navigation -- Same/Different Concept: An Embodied Spiking Neural Model in a Learning Context -- 1 Introduction -- 2 Methodology -- 2.1 Protocol -- 2.2 Neural Architecture -- 2.3 Physical Environment -- 3 Results -- 4 Discussion -- 5 Conclusion -- References -- Sparse and Topological Coding for Visual Localization of Autonomous Vehicles -- 1 Introduction -- 2 Related Work: Definition of the Sparse Coding -- 3 Topological Sparse Coding -- 4 SMP Model -- 5 Materials and Methods -- 5.1 Dataset -- 5.2 Metrics -- 5.3 Evaluation Methodology -- 5.4 Implementation Details -- 6 Results -- 6.1 Properties of TSC During Learning -- 6.2 Evaluation of Configuration/Performance -- 6.3 Evaluation of Localization Performances with the State of the Art -- 7 Discussion and Conclusion -- References -- Contribution of the Retrosplenial Cortex to Path Integration and Spatial Codes -- 1 Introduction -- 2 Computational Model -- 3 Experiment and Results -- 3.1 Recording ot Neurons Learning MD Activities in RSC -- 3.2 Building Place Cells from PI Information -- 3.3 Robustness of the Model -- 4 Conclusion and Perspective -- References.
Flexible Path Planning in a Spiking Model of Replay and Vicarious Trial and Error -- 1 Introduction -- 2 Methods -- 2.1 Spiking Wave Propagation -- 2.2 E-Prop and Back-Propagation Through Time -- 2.3 Extracting a Path from the Spike Wavefront Algorithm -- 3 Results -- 3.1 Simulating Human Navigation and Taking Novel Shortcuts -- 3.2 Simulating Rodent Navigation in Tolman Detour Task -- 4 Discussion -- References -- Affective and Social Cognition and Collective Intelligence -- Impact of the Update Time on the Aggregation of Robotic Swarms Through Informed Robots -- 1 Introduction -- 2 Materials and Methods -- 3 Results -- 4 Conclusions -- References -- On the Adaptive Value of Mood and Mood Contagion -- 1 Introduction -- 2 Agent Model -- 3 Reference Mood Experiments -- 4 Evolution of Mood -- 5 Mood Contagion -- 6 Evolution of Mood Contagion -- 7 Discussion -- References -- Author Index.
Record Nr. UNINA-9910592993403321
Cham, Switzerland : , : Springer Nature Switzerland AG, , [2022]
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