Pubbl/distr/stampa	Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 2018
Descrizione fisica	1 online resource (774 pages)
Disciplina	621.39732
Soggetto topico	Semiconductor storage devices Random access memory
ISBN	1-5386-5247-1
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Record Nr.	UNINA-9910280917203321

Autore	Yuan Fei
Edizione	[1st ed. 2020.]
Pubbl/distr/stampa	Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020
Descrizione fisica	1 online resource (238 pages)
Disciplina	621.3815 621.39732
Soggetto topico	Electronic circuits Signal processing Image processing Speech processing systems Electronics Microelectronics Circuits and Systems Signal, Image and Speech Processing Electronics and Microelectronics, Instrumentation
ISBN	3-030-17364-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Chapter 1. Injection-Locking of Oscillators : An Overview -- Chapter 2. Injection-Locking of Harmonic Oscillators -- Chapter 3. Injection-Locking Techniques for Harmonic Oscillators -- Chapter 4. Injection-Locking of Nonharmonic Oscillators -- Chapter 5. Injection-Locking Techniques for Nonharmonic Oscillators.
Record Nr.	UNINA-9910366582503321

Autore	Philippe Bart
Pubbl/distr/stampa	Cham, Switzerland : , : Springer, , [2022]
Descrizione fisica	1 online resource (145 pages)
Disciplina	621.39732
Collana	Analog Circuits and Signal Processing
Soggetto topico	Metal oxide semiconductors, Complementary Metal oxide semiconductors, Complementary - Design
ISBN	3-031-11224-5
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Intro -- Preface -- Contents -- Acronyms and Symbols -- 1 Introduction -- 1.1 Toward the Sixth-Generation (6G) Mobile Networks -- 1.1.1 Millimeter Wave to Increase Data Rates -- 1.2 Millimeter Wave in FinFET CMOS, the Next Step -- 1.3 Book Outline -- References -- 2 Basic Components in mm-Wave Design -- 2.1 Actives -- 2.1.1 fT, fmax a FoM for mm-Wave Transistors -- 2.1.2 The Effect of Scaling -- mm-Wave in FinFET -- 2.1.3 Transistor Layout and mm-Wave Performance -- 2.2 Passives -- 2.2.1 Capacitors -- 2.2.2 Inductors -- 2.2.3 Transformers -- 2.2.3.1 Transformer Topology -- 2.2.4 Transmission Lines -- 2.3 Basic Design of mm-Wave Circuits -- 2.3.1 A Capacitive Neutralized mm-Wave Amplifier -- 2.3.2 Design of mm-Wave Interconnects -- 2.3.2.1 Transformer Matching: A Coupled RLC Resonator -- 2.4 Conclusion -- References -- 3 Frequency Generation -- 3.1 VCO Basics -- 3.1.1 Brief on Phase Noise -- 3.1.2 Frequency Tuning -- 3.1.2.1 Varactor Tuning -- 3.1.2.2 Switched Capacitors -- 3.1.2.3 Switched Inductors -- 3.2 LO Architectures and Trends at mm-Wave -- 3.3 Challenges of a Deeply Scaled Technology at mm-Wave -- 3.4 A 4th Order Transformer-Based Resonator -- 3.5 Design Example: A Fundamental Oscillator -- 3.5.1 The Cross-Coupled Pair -- 3.5.2 The Resonator Design -- 3.5.3 Measurement Results -- 3.6 Design Example: A Harmonic Oscillator -- 3.6.1 Basic Principle -- 3.6.2 Proposed Design -- 3.6.3 Output Buffers -- 3.6.3.1 Fundamental Buffer -- 3.6.3.2 Third Harmonic Buffer -- 3.6.4 Measurement Results -- 3.7 Conclusion -- References -- 4 Power Amplification -- 4.1 Introduction -- 4.2 Power Amplifier Basics -- 4.2.1 Gain and Power -- 4.2.2 Efficiency -- 4.2.3 PA Linearity -- 4.2.4 PA Classes and Biasing -- 4.2.5 Challenge at mm-Wave in a Deeply Scaled Technology -- 4.2.5.1 The Effect of Drain Resistance -- 4.2.5.2 Limits on Output Power. 4.3 Design Example: A Class-A Two-Way Power Combining D-Band PA in 16nm FinFET -- 4.3.1 Design of the 16nm FinFET Transistor -- 4.3.2 Build-up of the Power Amplifier -- 4.3.2.1 Power Combining to Extend the Power Limit -- 4.3.2.2 Completing the Circuit with Drivers -- 4.3.3 Measurement Results -- 4.4 Conclusion -- References -- 5 A D-band Direct-Conversion Transmitter with Enhanced PA -- 5.1 Efficiency Enhancement Techniques -- 5.1.1 Common Efficiency Enhancement Techniques -- 5.1.1.1 Doherty Power Amplifier -- 5.1.1.2 Outphasing PA -- 5.1.1.3 Conclusion: Difficulties for > -- 100 GHz Power Amplifiers -- 5.1.2 A Sequential Power Amplifier -- 5.1.3 Conclusion -- 5.2 Linearization Techniques by Dynamic Bias -- 5.2.1 AM-AM Compensation -- 5.2.2 AM-PM Compensation -- 5.2.2.1 Capacitive Compensation -- 5.2.2.2 Fixed Phase Offset -- 5.3 Design Example: A Direct-Conversion TX with Enhanced PA -- 5.3.1 The Dynamic Bias Enhanced PA -- 5.3.1.1 Amplifier Stages and Interstage Matching -- 5.3.1.2 The Dynamic Bias Circuit -- 5.3.1.3 AM-PM Control -- 5.3.1.4 PA Simulation Results -- 5.3.2 The I/Q Modulator and LO Generation -- 5.3.2.1 Quadrature LO Circuit -- 5.3.2.2 The Double Balanced IQ-Mixer -- 5.4 Measurements and Discussion -- 5.4.1 Power Amplifier Measurements -- 5.4.1.1 Small-Signal Measurement -- 5.4.1.2 Large Signal Measurement -- 5.4.1.3 Conclusion PA Measurements -- 5.4.2 Transmitter Measurements -- 5.4.2.1 Continuous Wave Measurements and Characterization -- 5.4.2.2 Modulated Data Measurements -- 5.5 Conclusion -- References -- Index.
Record Nr.	UNINA-9910627270203321

Autore	Kursun Volkan
Pubbl/distr/stampa	Chichester, England ; ; Hoboken, NJ, : John Wiley, 2006
Descrizione fisica	1 online resource (243 p.)
Disciplina	621.39732
Altri autori (Persone)	FriedmanEby G
Soggetto topico	Metal oxide semiconductors, Complementary Low voltage integrated circuits - Design and construction
ISBN	1-280-64869-4 9786610648696 0-470-03337-1 0-470-01024-X
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	Multi-voltage CMOS Circuit Design; Contents; About the Authors; Preface; Acknowledgments; Chapter 1 Introduction; 1.1 Evolution of Integrated Circuits; 1.2 Outline of the Book; Chapter 2 Sources of Power Consumption in CMOS ICs; 2.1 Dynamic Switching Power; 2.2 Leakage Power; 2.2.1 Subthreshold Leakage Current; 2.2.1.1 Short-Channel Effects; 2.2.1.2 Drain-Induced Barrier-Lowering; 2.2.1.3 Characterization of Subthreshold Leakage Current; 2.2.2 Gate Oxide Leakage Current; 2.2.2.1 Effect of Technology Scaling on Gate Oxide Leakage; 2.2.2.2 Characterization of Gate Oxide Leakage Current 2.2.2.3 Alternative Gate Dielectric Materials2.3 Short-Circuit Power; 2.4 Static DC Power; Chapter 3 Supply and Threshold Voltage Scaling Techniques; 3.1 Dynamic Supply Voltage Scaling; 3.2 Multiple Supply Voltage CMOS; 3.3 Threshold Voltage Scaling; 3.3.1 Body Bias Techniques; 3.3.1.1 Reverse Body Bias; 3.3.1.2 Forward Body Bias; 3.3.1.3 Bidirectional Body Bias; 3.3.2 Multiple Threshold Voltage CMOS; 3.4 Multiple Supply and Threshold Voltage CMOS; 3.5 Dynamic Supply and Threshold Voltage Scaling; 3.6 Circuits with Multiple Voltage and Clock Domains; 3.7 Summary Chapter 4 Low-Voltage Power Supplies4.1 Linear DC-DC Converters; 4.2 Switched-Capacitor DC-DC Converters; 4.3 Switching DC-DC Converters; 4.3.1 Operation of a Buck Converter; 4.3.2 Power Reduction Techniques for Switching DC-DC Converters; 4.4 Summary; Chapter 5 Buck Converters for On-Chip Integration; 5.1 Circuit Model of a Buck Converter; 5.1.1 MOSFET-Related Power Losses; 5.1.2 Filter Inductor-Related Power Losses; 5.1.3 Filter Capacitor-Related Power Losses; 5.1.4 Total Power Consumption of a Buck Converter; 5.2 Efficiency Analysis of a Buck Converter 5.2.1 Circuit Analysis for Global Maximum Efficiency5.2.2 Circuit Analysis with Limited Filter Capacitance; 5.2.3 Output Voltage Ripple Constraint; 5.3 Simulation Results; 5.4 Summary; Chapter 6 Low-Voltage Swing Monolithic DC-DC Conversion; 6.1 Circuit Model of a Low-Voltage Swing Buck Converter; 6.1.1 MOSFET Power Dissipation; 6.1.2 MOSFET Model; 6.1.3 Filter Inductor Power Dissipation; 6.2 Low-Voltage Swing Buck Converter Analysis; 6.2.1 Full Swing Circuit Analysis for Global Maximum Efficiency; 6.2.2 Low Swing Circuit Analysis for Global Maximum Efficiency; 6.3 Summary Chapter 7 High Input Voltage Step-Down DC-DC Converters7.1 Cascode Bridge Circuits; 7.1.1 Cascode Bridge Circuit for Input Voltages up to 2Vmax; 7.1.2 Cascode Bridge Circuit for Input Voltages up to 3Vmax; 7.1.3 Cascode Bridge Circuit for Input Voltages up to 4Vmax; 7.2 High Input Voltage Monolithic Switching DC-DC Converters; 7.2.1 Operation of Cascode DC-DC Converters; 7.2.2 Efficiency Characteristics of DC-DC Converters Operating at Input Voltages up to 2Vmax; 7.2.3 Efficiency Characteristics of DC-DC Converters Operating at Input Voltages up to 3Vmax; 7.3 Summary Chapter 8 Signal Transfer in ICs with Multiple Supply Voltages
Record Nr.	UNINA-9910143684103321

Pubbl/distr/stampa	Hoboken, NJ, : Wiley, c2009
Descrizione fisica	1 online resource (403 p.)
Disciplina	621.39/5 621.39732
Altri autori (Persone)	WongBan P. <1953->
Soggetto topico	Metal oxide semiconductors, Complementary - Design and construction Integrated circuits - Design and construction Nanoelectronics
Soggetto genere / forma	Electronic books.
ISBN	1-282-68822-7 9786612688225 0-470-38282-1 1-61583-175-4 0-470-38281-3
Formato	Materiale a stampa
Livello bibliografico	Monografia
Lingua di pubblicazione	eng
Nota di contenuto	NANO-CMOS DESIGN FOR MANUFACTURABILILTY; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1 Introduction; 1.1 Value of Design for Manufacturability; 1.2 Deficiencies in Boolean-Based Design Rules in the Subwavelength Regime; 1.3 Impact of Variability on Yield and Performance; 1.4 Industry Challenge: The Disappearing Process Window; 1.5 Mobility Enhancement Techniques: A New Source of Variability Induced by Design-Process Interaction; 1.6 Design Dependency of Chip Surface Topology; 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes; 1.8 Well Proximity Effect 1.9 Need for Model-Based DFM Solutions Beyond 65 nm1.10 Summary; References; I NEWLY EXACERBATED EFFECTS; 2 Lithography-Related Aspects of DFM; 2.1 Economic Motivations for DFM; 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes; 2.2.1 Lithographic Approaches to Sub-90-nm Lithography; 2.2.2 Lithographic Infrastructure; 2.2.3 Immersion Exposure Tools; 2.2.4 Overlay; 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization; 2.2.6 Optical Proximity Correction; 2.2.7 Double Patterning; 2.2.8 Lithographic Roadmap; 2.3 Lithography Limited Yield 2.3.1 Deviations of Printed Shape from Drawn Polygon2.3.2 Increased Variabilities; 2.3.3 Catastrophic Failures; 2.4 Lithography-Driven DFM Solutions; 2.4.1 Practical Boundary Conditions for DFM; 2.4.2 Classical Approach; 2.4.3 Printability Checkers; 2.4.4 Model-Based Design Rule Checks; 2.4.5 ASIC Cell Optimizations; 2.4.6 Lithography-Aware Routers; 2.4.7 Advanced OPC Techniques for Improved Manufacturing; References; 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques; 3.1 Introduction; 3.2 Impact of Stress on Transistor Performance; 3.2.1 Electron Mobility 3.2.2 Hole Mobility3.2.3 Threshold Voltage; 3.2.4 Junction Leakage; 3.2.5 High Stress Levels; 3.2.6 Crystal Orientations; 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns; 3.2.8 Stress Gradients; 3.2.9 Effects of Temperature and High Dopant Concentrations; 3.2.10 Stress Effects in Nonsilicon Semiconductors; 3.3 Stress Propagation; 3.3.1 Stress Propagation for Various Stress Source Geometries; 3.3.2 Stress Propagation Through STI and Other Barriers; 3.3.3 Free Boundaries; 3.4 Stress Sources; 3.4.1 Thermal Mismatch: STI and Silicide; 3.4.2 Lattice Mismatch: eSiGe and Si : C 3.4.3 Layer Growth3.4.4 Intrinsic Stress: CESL and DSL; 3.4.5 Stress Memorization Technique; 3.4.6 Stress Measurement Techniques; 3.4.7 Stress Simulation Techniques; 3.5 Introducing Stress into Transistors; 3.5.1 Stress Evolution During Process Flow; 3.5.2 Stress Relaxation Mechanisms; 3.5.3 Combining Several Stress Sources; 3.5.4 Stress-Engineered Memory Retention; 3.5.5 Layout-Induced Variations; 3.5.6 Bulk Transistors versus SOI and FinFET; References; II DESIGN SOLUTIONS; 4 Signal and Power Integrity; 4.1 Introduction; 4.2 Interconnect Resistance, Capacitance, and Inductance 4.2.1 Process Scaling and Interconnect Fabrication
Record Nr.	UNINA-9910144431403321