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CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam
| CMOS voltage references : an analytical and practical perspective / / Chi-Wah Kok and Wing-Shan Tam |
| Autore | Kok Chi-Wah |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | [Hoboken, New Jersey] : , : Wiley, , 2012 |
| Descrizione fisica | 1 online resource (312 p.) |
| Disciplina |
621.381528
621.39732 |
| Altri autori (Persone) | TamWing-Shan |
| Soggetto topico |
Voltage references
Electric circuit analysis Electric circuits - Design and construction |
| ISBN |
1-118-27569-1
1-283-86962-4 1-118-27570-5 |
| Classificazione | TEC008010 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Front Matter -- Warm Up -- Voltage Reference -- Bandgap Voltage Reference -- Error Sources in Bandgap Voltage Reference Circuit -- Advanced Voltage Reference Circuits. Temperature Compensation Techniques -- Sub-1V Voltage Reference Circuit -- High Order Curvature Correction -- CMOS Voltage Reference without Resistors -- SPICE Model File -- SPICE Netlist of Voltage Reference Circuit -- Index |
| Record Nr. | UNINA-9910830590803321 |
Kok Chi-Wah
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| [Hoboken, New Jersey] : , : Wiley, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Continuous-time digital front-ends for multistandard wireless transmission / / Pieter A.J. Nuyts, Patrick Reynaert, Wim Dehaene
| Continuous-time digital front-ends for multistandard wireless transmission / / Pieter A.J. Nuyts, Patrick Reynaert, Wim Dehaene |
| Autore | Nuyts Pieter A. J |
| Edizione | [1st ed. 2014.] |
| Pubbl/distr/stampa | Cham, Switzerland : , : Springer, , 2014 |
| Descrizione fisica | 1 online resource (xxv, 309 pages) : illustrations |
| Disciplina | 621.39732 |
| Collana | Analog Circuits and Signal Processing |
| Soggetto topico | Digital integrated circuits |
| ISBN | 3-319-03925-3 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Digital Transmitter Architectures: Overview -- High-Level Analysis of Fully Digital PWM Transmitters -- Continuous-time Digital Design Techniques -- A 65-nm CMOS Fully Digital Reconfigurable Transmitter Front-End for Class-E PA based on Baseband PWM -- A 40-nm CMOS Fully Digital Reconfigurable Transmitter with Class-D Pas using Baseband and RF PWM -- Conclusions and Future Work. |
| Record Nr. | UNINA-9910299481703321 |
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Nuyts Pieter A. J
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| Cham, Switzerland : , : Springer, , 2014 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| Soggetto genere / forma | Electronic books. |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910457087103321 |
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Yanda Richard F
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| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking [[electronic resource] /] / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910784359603321 |
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Yanda Richard F
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| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Demystifying chipmaking / / by Richard F. Yanda, Michael Heynes and Anne K. Miller
| Demystifying chipmaking / / by Richard F. Yanda, Michael Heynes and Anne K. Miller |
| Autore | Yanda Richard F |
| Edizione | [1st ed.] |
| Pubbl/distr/stampa | Oxford, : Newnes |
| Descrizione fisica | 1 online resource (276 p.) |
| Disciplina | 621.39732 |
| Altri autori (Persone) |
HeynesMichael
MillerAnne K |
| Soggetto topico |
Logic circuits - Design and construction
Metal oxide semiconductors, Complementary |
| ISBN |
1-281-00979-2
9786611009793 0-08-047709-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto |
Cover; Contents; Foreword; Acknowledgments; About the Authors; Chapter 1: IC Fabrication Overview; Section 1: Introduction; 1.1 Integrated Circuits; 1.2 The Semiconductor Industry; Section 2: Support Technologies; 2.1 Crystal Growth and Wafer Preparation; 2.2 Contamination Control; 2.3 Circuit Design and Mask Making; 2.4 Process Diagnostics and Metrology; Section 3: Integrated Circuit Fabrication; 3.1 Layering; 3.2 Patterning; 3.3 Doping; 3.4 Process Control and In-line Monitoring; Section 4: Test and Assembly; 4.1 Electrical Tests; 4.2 Die Separation; 4.3 Die Attach and Wire Bonding
4.4 Encapsulation4.5 Final Test; Section 5: Summary; Chapter 2: Support Technologies; Section 1: Introduction; Section 2: Contamination Control; 2.1 Why Control Contamination?; 2.2 Contamination Sources; 2.3 The Cleanroom; Section 3: Crystal Growth and Wafer Preparation; 3.1 Introduction; 3.2 Silicon Purification; 3.3 Czochralski Silicon Growth; 3.4 Shaping, Grinding, Cutting and Polishing; 3.5 Final Inspection and Shipping; Section 4: Circuit Design; 4.1 Introduction; 4.2 Product Definition and New Product Plan; 4.3 The Design Team; 4.4 The Design Process; 4.5 Design Verification and Tapeout Section 5: Photomask and Reticle Preparation5.1 Introduction; 5.2 Reticle Substrate Preparation; 5.3 Pattern Transfer; 5.4 Inspection and Defect Repair; Chapter 3: Forming Wells; Section 1: Introduction; Section 2: Initial Oxidation; Section 3: Photolithography; 3.1 Introduction; 3.2 Coat (Spin); 3.3 Exposure (Step); 3.4 Develop; 3.5 After Develop Inspect (ADI); Section 4: Ion Implantation; Chapter 4: Isolate Active Areas (Shallow Trench Isolation); Section 1: Introduction to Shallow Trench Isolation; Section 2: Pad Oxide Growth; Section 3: Silicon Nitride Deposition Section 4: Photolithography for Photo/EtchSection 5: Hard Mask Formation Using Plasma Etch; 5.1 Hard Mask Overview; 5.2 Plasma Etch Overview; 5.3 Etch Chemistry: Silicon Dioxide and Silicon Nitride; Section 6: Form Trenches in Silicon with Plasma Etch; Section 7: Fill Trenches with Silicon Dioxide; Section 8: Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide; Section 9: Wet Etch Removal of Silicon Nitride and Pad Oxide; Chapter 5: Building the Transistors; Section 1: Introduction; Section 2: Thin Film Formation; 2.1 Gate Dielectric Oxidation 2.2 Polycrystalline Silicon (Poly) Deposition2.3 Nitride Cap Deposition; Section 3: Poly Gate Formation; 3.1 Photoresist Patterning; 3.2 Plasma Etch; Section 4: Source/Drain Formation; 4.1 Introduction; 4.2 Shallow Implant; 4.3 Spacer Formation; 4.4 High-Dose Implant; 4.5 Anneal; Section 5: Salicide Formation; 5.1 Sputter Cobalt; 5.2 RTP Reaction Forming Silicide; 5.3 Strip Residual Cobalt; 5.4 Anneal the Silicide; Chapter 6: First Level Metallization; Section 1: Introduction; Section 2: Nitride and Oxide Depositions; 2.1 Nitride Deposition; 2.2 Oxide Deposition; Section 3: CMP Planarization Section 4: Photo/Etch for Contact Holes |
| Record Nr. | UNINA-9910825105903321 |
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Yanda Richard F
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| Oxford, : Newnes | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Design of analog CMOS integrated circuits / Behzad Razavi
| Design of analog CMOS integrated circuits / Behzad Razavi |
| Autore | Razavi, Behzad |
| Edizione | [International ed] |
| Pubbl/distr/stampa | Boston \etc.!, : McGraw-Hill, \2001! |
| Descrizione fisica | XX, 684 p. ; 23 cm. |
| Disciplina | 621.39732 |
| Collana | McGraw-Hill series in electrical and computer engineering |
| Soggetto non controllato |
Circuiti integrati MOS
Semiconduttori |
| ISBN |
0071188150
0071188398 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNINA-9910721501303321 |
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Razavi, Behzad
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| Boston \etc.!, : McGraw-Hill, \2001! | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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The design of CMOS radio-frequency integrated circuits / Thomas H. Lee
| The design of CMOS radio-frequency integrated circuits / Thomas H. Lee |
| Autore | Lee, Thomas H., 1959- |
| Edizione | [2nd ed.] |
| Pubbl/distr/stampa | Cambridge, UK ; New York : Cambridge University Press, 2004 |
| Descrizione fisica | xviii, 797 p. : ill. ; 26 cm |
| Disciplina | 621.39732 |
| Soggetto topico |
Metal oxide semiconductors, Complementary - Design and construction
Radio frequency integrated circuits - Design and construction Radio - Transmitter-receivers |
| ISBN | 0521835399 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISALENTO-991003929129707536 |
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Lee, Thomas H., 1959-
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| Cambridge, UK ; New York : Cambridge University Press, 2004 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. del Salento | ||
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Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations / / edited by Hideto Hidaka
| Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations / / edited by Hideto Hidaka |
| Edizione | [1st ed. 2018.] |
| Pubbl/distr/stampa | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
| Descrizione fisica | 1 online resource (VIII, 247 p. 262 illus., 192 illus. in color.) |
| Disciplina | 621.39732 |
| Collana | Integrated Circuits and Systems |
| Soggetto topico |
Electronic circuits
Microprocessors Computer memory systems Circuits and Systems Electronic Circuits and Devices Processor Architectures Memory Structures |
| ISBN | 3-319-55306-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Introduction -- Applications and Technology Trend in Embedded Flash Memory -- Overview of Embedded Flash Memory Technology -- Floating-gate 1Tr-NOR eFlash memory -- Split-Gate Floating Poly SuperFlash Memory Technology, Design and Reliability -- SONOS 1Tr eFlash memory -- SONOS split-gate eFlash memory. |
| Record Nr. | UNINA-9910299926203321 |
| Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Emerging non-volatile memory technologies : physics, engineering, and applications / / Wen Siang Lew, Gerard Joseph Lim, Putu Andhita Dananjaya, editors
| Emerging non-volatile memory technologies : physics, engineering, and applications / / Wen Siang Lew, Gerard Joseph Lim, Putu Andhita Dananjaya, editors |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (VIII, 438 p. 254 illus., 231 illus. in color.) |
| Disciplina | 621.39732 |
| Soggetto topico | Nonvolatile random-access memory - Technological innovations |
| ISBN | 981-15-6912-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Microwave Oscillators and Detectors Based on Magnetic Tunnel Junctions -- Spin Transfer Torque Magnetoresistive Random Access Memory -- Current-Driven Domain Wall Dynamics in Magnetic Heterostructures for Memory Applications -- Electric-field-controlled MRAM: Physics and Applications -- Chiral Magnetic Domain Wall & Skyrmion Memory Devices -- Circuit Design for Non-volatile Magnetic Memory -- Domain Wall Programmable Magnetic Logic -- 3D Nanomagnetic Logic -- Spintronics for Neuromorphic Engineering -- Resistive Random Access Memory: Device Physics and Array Architectures -- RRAM Characterization and Modelling -- RRAM-based Neuromorphic Computing Systems -- An Automatic Sound Classification Framework with Non-Volatile Memory. |
| Record Nr. | UNINA-9910483710403321 |
| Singapore : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
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Emerging non-volatile memory technologies : physics, engineering, and applications / / Wen Siang Lew, Gerard Joseph Lim, Putu Andhita Dananjaya, editors
| Emerging non-volatile memory technologies : physics, engineering, and applications / / Wen Siang Lew, Gerard Joseph Lim, Putu Andhita Dananjaya, editors |
| Edizione | [1st ed. 2021.] |
| Pubbl/distr/stampa | Singapore : , : Springer, , [2021] |
| Descrizione fisica | 1 online resource (VIII, 438 p. 254 illus., 231 illus. in color.) |
| Disciplina | 621.39732 |
| Soggetto topico | Nonvolatile random-access memory - Technological innovations |
| ISBN | 981-15-6912-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Microwave Oscillators and Detectors Based on Magnetic Tunnel Junctions -- Spin Transfer Torque Magnetoresistive Random Access Memory -- Current-Driven Domain Wall Dynamics in Magnetic Heterostructures for Memory Applications -- Electric-field-controlled MRAM: Physics and Applications -- Chiral Magnetic Domain Wall & Skyrmion Memory Devices -- Circuit Design for Non-volatile Magnetic Memory -- Domain Wall Programmable Magnetic Logic -- 3D Nanomagnetic Logic -- Spintronics for Neuromorphic Engineering -- Resistive Random Access Memory: Device Physics and Array Architectures -- RRAM Characterization and Modelling -- RRAM-based Neuromorphic Computing Systems -- An Automatic Sound Classification Framework with Non-Volatile Memory. |
| Record Nr. | UNISA-996466751903316 |
| Singapore : , : Springer, , [2021] | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
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