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Biblioteca

MARC Lista (tabellare)
Modern electronic instrumentation and measurement techniques / Albert D. Helfrick, William D. Cooper
Modern electronic instrumentation and measurement techniques / Albert D. Helfrick, William D. Cooper
Autore Helfrick, Albert D.
Pubbl/distr/stampa Englewood Cliffs : Prentice-Hall international, c1990
Descrizione fisica XII, 446 p. : ill. ; 23 cm
Disciplina 621.381548
Altri autori (Persone) Cooper, William D.
Soggetto non controllato Misure elettroniche - Strumenti
ISBN 0135933854
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNIPARTHENOPE-000011564
Helfrick, Albert D.  
Englewood Cliffs : Prentice-Hall international, c1990
Materiale a stampa
Lo trovi qui: Univ. Parthenope
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Proceedings International Test Conference 1997 / / Institute of Electrical and Electronics Engineers
Proceedings International Test Conference 1997 / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Washington, D.C. : , : IEEE, , 1997
Descrizione fisica 1 online resource (xiv, 1054 pages) : illustrations
Disciplina 621.381548
Soggetto topico Integrated circuits - Testing
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996199315403316
Washington, D.C. : , : IEEE, , 1997
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Sensori e trasduttori per industria e automazione : guida pratica / Emilio Carnevale
Sensori e trasduttori per industria e automazione : guida pratica / Emilio Carnevale
Autore Carnevale, Emilio
Edizione [2. ed.]
Pubbl/distr/stampa Tricase : Youcanprint, c[2017]
Descrizione fisica 168 p : ill. ; 22 cm
Disciplina 621.381548
Soggetto topico Measuring instruments
Electronic instruments
ISBN 9788892681088
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione ita
Record Nr. UNISALENTO-991003993339707536
Carnevale, Emilio  
Tricase : Youcanprint, c[2017]
Materiale a stampa
Lo trovi qui: Univ. del Salento
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SICE '99 : proceedings of the 38th SICE Annual Conference : international session papers : Iwate University, July 28-30, 1999 / / Institute of Electrical and Electronics Engineers
SICE '99 : proceedings of the 38th SICE Annual Conference : international session papers : Iwate University, July 28-30, 1999 / / Institute of Electrical and Electronics Engineers
Pubbl/distr/stampa Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1999
Descrizione fisica 1 online resource (1238 pages)
Disciplina 621.381548
Soggetto topico Electronic instruments
Automatic control
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Record Nr. UNISA-996199965503316
Piscataway, New Jersey : , : Institute of Electrical and Electronics Engineers, , 1999
Materiale a stampa
Lo trovi qui: Univ. di Salerno
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Spectrum and network measurements / Robert A. Witte ; with additions to Chapter 4 by the Lake Stevens Instrument Division of Hewlett-Packard Company
Spectrum and network measurements / Robert A. Witte ; with additions to Chapter 4 by the Lake Stevens Instrument Division of Hewlett-Packard Company
Autore Witte, Robert A.
Pubbl/distr/stampa Englewood Cliffs (N.J.), : Prentice Hall PTR, c1993
Descrizione fisica XV, 297 p. : ill. ; 24 cm.
Disciplina 621.3815
621.381548
Soggetto topico Strumenti elettronici per misure
ISBN 0130308005
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Altri titoli varianti Spectrum & network measurements
Record Nr. UNISANNIO-RMS0031679
Witte, Robert A.  
Englewood Cliffs (N.J.), : Prentice Hall PTR, c1993
Materiale a stampa
Lo trovi qui: Univ. del Sannio
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Structural Decision Diagrams in Digital Test : Theory and Applications
Structural Decision Diagrams in Digital Test : Theory and Applications
Autore Ubar Raimund
Edizione [1st ed.]
Pubbl/distr/stampa Cham : , : Springer International Publishing AG, , 2024
Descrizione fisica 1 online resource (608 pages)
Disciplina 621.381548
Altri autori (Persone) RaikJaan
JenihhinMaksim
JutmanArtur
Collana Computer Science Foundations and Applied Logic Series
ISBN 3-031-44734-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Intro -- Preface -- The Idea -- Acknowledgements -- Contents -- 1 Introduction -- 2 Overview of Structural Decision Diagrams -- 2.1 A Short History of Structural Decision Diagrams -- 2.1.1 Binary Decision Diagrams -- 2.1.2 Logic-Level Structural Decision Diagrams -- 2.1.3 High-Level Decision Diagrams -- 2.2 Binary Decision Diagrams -- 2.3 Structurally Synthesized Binary Decision Diagrams -- 2.4 Shared Structurally Synthesized BDDs -- 2.5 High-Level Decision Diagrams -- 2.5.1 About the Similarity of Low- and High-Level Structural DDs -- 2.5.2 RTL Modeling of Digital Modules with HLDDs -- 2.5.3 RTL Modeling of Control Circuits with HLDDs -- 2.5.4 Instruction-Level Modeling of Microprocessors -- 2.6 Structural DDs as a Universal Tool for Digital Test -- 3 Structurally Synthesized BDDs -- 3.1 Synthesis of SSBDDs -- 3.1.1 Definition of SSBDD -- 3.1.2 Synthesis of the SSBDD Model for a Digital Circuit -- 3.1.3 Verification of the Correctness of SSBDDs -- 3.2 Properties and Specific Features of SSBDDs -- 3.2.1 Basic Operations on SSBDDs -- 3.2.2 Basic Properties of SSBDD -- 3.2.3 SSBDDs and Boolean Algebra -- 3.2.4 SSBDDs and Functional BDDs -- 3.3 Equivalent Transformations of SSBDDs -- 3.3.1 Mapping Between SSBDDs and FFRs of Digital Circuits -- 3.3.2 Restructuring of SSBDDs to Speed-Up Simulation -- 3.3.3 Optimization of SSBDDs by Reconfiguring the Structure -- 3.3.4 Restructuring of SSBDDs for Sharing the Sub-graphs -- 3.4 Shared Structurally Synthesized BDD -- 3.4.1 Definitions and the Structure of S3BDDs -- 3.4.2 Synthesis of S3BDDs -- 3.4.3 The Size of the S3BDD Model -- 4 Fault Modelling with Structural BDDs -- 4.1 Fault Modeling with Structural BDDs -- 4.1.1 Modeling Faults with SSBDDs -- 4.1.2 Measuring Fault Coverage Using SSBDDs -- 4.1.3 Modeling Faults with S3BDDs -- 4.1.4 Mapping of S3BDD Nodes to Signal Paths in Circuits.
4.1.5 Making Faults Observable in S3BDDs -- 4.1.6 Modeling Path and Path Segment Delay Faults in S3BDDs -- 4.2 Extending the Class of Faults -- 4.2.1 Generalization of the SAF Model -- 4.2.2 Modeling Physical Defects by Boolean Differential Equations -- 4.2.3 Hierarchical Fault Modeling Using Conditional SAF -- 4.3 Fault Collapsing -- 4.3.1 Related Work and Definitions -- 4.3.2 Fault Equivalence and Fault Dominance in the SSBDD Model -- 4.3.3 Fault Collapsing in SSBDDs -- 5 Logic-Level Fault Simulation -- 5.1 Fault-Free Logic Simulation -- 5.1.1 Fault-Free Simulation with Structural BDDs -- 5.1.2 Multi-valued Logic Simulation with SSBDDs -- 5.2 Fault Simulation in Combinational Circuits -- 5.2.1 Related Work and Overview -- 5.2.2 Parallel Fault Simulation with SSBDDs -- 5.2.3 Critical Path Parallel Pattern Fault Backtracing -- 5.2.4 Fault Simulation for the Extended Class of Faults -- 5.2.5 Fault Simulation in Multiple Core Environments -- 5.3 Fault Simulation in Sequential Circuits -- 5.3.1 Combining Combinational and Sequential Simulation -- 5.3.2 Design for Testability for Fault Simulation in Sequential Circuits -- 5.4 Identification of Critical Paths with Logic Simulation -- 5.4.1 The Concept of True Critical Path Identification -- 5.4.2 Calculation of the Lengths of Sensitized Paths in Sequential Circuits with SSBDDs -- 5.4.3 Search for the Longest Critical Paths in Sequential Circuits -- 6 Test Generation, Testability and Fault Diagnosis -- 6.1 Test Generation Using Structural BDDs -- 6.1.1 Path Activation in SSBDDs -- 6.1.2 Test Pattern Generation with SSBDDs -- 6.1.3 Test Pattern Generation with S3BDDs -- 6.1.4 The Problem of Fault Masking -- 6.2 Test Pattern Generation for Multiple Faults with SSBDDs -- 6.2.1 Related Work -- 6.2.2 Contributions of the Method of Test Groups -- 6.2.3 The Problem of Fault Masking Revisited.
6.2.4 SSBDDs and the Topological View on the Fault Masking -- 6.2.5 The Concept of Test Groups -- 6.3 Testability Analysis of Digital Circuits with SSBDDs -- 6.3.1 Related Work and Overview -- 6.3.2 Calculation of Signal Probabilities in the Logic Circuits -- 6.3.3 Calculating the Probabilistic Controllability with SSBDDs -- 6.3.4 Controllability of Signals at Internal Nodes of FFRs -- 6.3.5 Discussion on Different Methods of Controllability Calculation -- 6.3.6 Experimental Research Results on Calculating Signal Probabilities -- 6.3.7 Concluding Remarks -- 6.4 Fault Diagnosis in the General Case of Multiple Faults -- 6.4.1 Angel's Advocate Approach to Fault Diagnosis -- 6.4.2 Boolean Differential Equations and Fault Diagnosis -- 6.4.3 A General Equation for Modeling Diagnostic Processes -- 6.4.4 Solving Boolean Differential Equations with SSBDDs -- 6.4.5 Test Groups and Hierarchical Fault Diagnosis -- 7 High-Level Decision Diagrams -- 7.1 Theoretical Basics of HLDDs -- 7.1.1 HLDDs as a Diagnostic Model for Digital Systems -- 7.1.2 Behavioral Level Synthesis of HLDDs -- 7.1.3 Structural Synthesis of HLDDs -- 7.1.4 Timed Superposition of DDs -- 7.2 High-Level DDs and Design Simulation -- 7.2.1 Simulation of Digital Systems with HLDDs -- 7.2.2 Vector High-Level Decision Diagrams -- 7.2.3 Code Coverage Measurement with HLDDs -- 7.2.4 Hierarchical Fault Simulation Combining SSBDDs and HLDDs -- 7.3 Hierarchical Multi-level Test Generation in Sequential Circuits with DDs -- 7.3.1 Related Work in Sequential Circuit Test Generation -- 7.3.2 Hierarchical Test Generation for Sequential Circuits -- 7.3.3 DECIDER -- 7.3.4 Untestability Identification in Sequential Circuits with HLDDs -- 8 HLDD-Based Test Generation for RISC Processors -- 8.1 Overview of High-Level Test Generation Concepts for Processors.
8.1.1 Fault Modeling of Digital Systems at Different Levels -- 8.1.2 Related Work on the Microprocessor Test -- 8.1.3 Research on Software-Based Self-test of Microprocessors -- 8.1.4 Contributions Beyond the State of the Art -- 8.2 High-Level Fault Modeling of Microprocessors with HLDDs -- 8.2.1 Fault Modeling as a Trade-off of Complexity Versus Accuracy -- 8.2.2 Traditional High-Level Fault Models for Digital Systems -- 8.2.3 HLDD-Based Functional Fault Model for RISC Processors -- 8.3 Implementation-Independent Control Fault Model for Processors -- 8.3.1 Partitioning of a RISC Processor into Modules -- 8.3.2 Theoretical Foundations of the Implementation-Independent Test -- 8.3.3 High-Level Control Fault Model of MUTs on HLDDs -- 8.3.4 Mixed-Level Identification of Fault Redundancy -- 8.3.5 Optimization of HLDDs and High-Level Fault Modeling Trade-offs -- 8.4 Extension of Fault Classes for Implementation-Independent Testing -- 8.4.1 Mapping of Low-Level Structural Faults to the High-Level Constraints-Based Fault Model -- 8.4.2 Extension of the Fault Classes with Implementation-Independent Testing -- 8.5 Test Data Generation for the Modules of RISC Processors -- 8.5.1 Test Data for Testing the Control Part of a MUT -- 8.5.2 Pseudo-exhaustive Test Generation for the Data Part -- 8.6 Software-Based Self-Test Synthesis -- 8.6.1 Organization of Test Programs and the Concept of Test Templates -- 8.6.2 Conformity and Scanning Tests for a MUT -- 8.6.3 Test Generation for Delay Faults -- 8.7 Multiple Fault Testing in Microprocessors Using HLDDs -- 8.7.1 Topological View on Decision Diagrams for Multiple Fault Reasoning -- 8.7.2 Merged Cycle-Based HLDD Model for Digital Systems -- 8.7.3 Test Generation for Microprocessors Avoiding Fault Masking -- References.
Record Nr. UNINA-9910806194603321
Ubar Raimund  
Cham : , : Springer International Publishing AG, , 2024
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Strumentazione di misura e controllo nelle applicazioni industriali / Brunelli, A.
Strumentazione di misura e controllo nelle applicazioni industriali / Brunelli, A.
Autore Brunelli, Alessandro
Pubbl/distr/stampa Milano : Gisi, stampa 1994-2000
Descrizione fisica 5 v. : ill. ; 24 cm
Disciplina 621.381548
Collana I quaderni del GISI
Soggetto topico Strumenti di misurazione nelle applicazioni industriali
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione ||
Nota di contenuto V.1 Caratteristiche generali sensori e trasduttori; v.2 Misura ; v.3-1 Controllo strumenti e sistemi; v.3-2 Controllo valvole e azionamenti; v.4 Normativa e terminologia, indice analitico
Record Nr. UNISALENTO-991003067079707536
Brunelli, Alessandro  
Milano : Gisi, stampa 1994-2000
Materiale a stampa
Lo trovi qui: Univ. del Salento
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Strumentazione elettronica di misura / Domenico Mirri ; in collaborazione con Gaetano Pasini
Strumentazione elettronica di misura / Domenico Mirri ; in collaborazione con Gaetano Pasini
Autore Mirri, Domenico
Edizione [2. ed.]
Pubbl/distr/stampa Padova : CEDAM, 2004
Descrizione fisica XV, 337 p. : ill. ; 24 cm
Disciplina 621.381548
Soggetto non controllato Strumenti elettronici per misure
ISBN 978-88-1325-076-8
88-13-25076-2
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione ita
Record Nr. UNINA-990008364810403321
Mirri, Domenico  
Padova : CEDAM, 2004
Materiale a stampa
Lo trovi qui: Univ. Federico II
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Strumentazione elettronica di misura / Domenico Mirri ; in collaborazione con Gaetano Pasini
Strumentazione elettronica di misura / Domenico Mirri ; in collaborazione con Gaetano Pasini
Autore Mirri, Domenico
Edizione [2. ed.]
Pubbl/distr/stampa Padova : Cedam, c2004
Descrizione fisica xv, 337 p : ill. ; 26 cm
Disciplina 621.381548
Altri autori (Persone) Pasini, Gaetano
Soggetto topico Measuring instruments
Electronic instruments
ISBN 8813250762
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione ita
Record Nr. UNISALENTO-991000417519707536
Mirri, Domenico  
Padova : Cedam, c2004
Materiale a stampa
Lo trovi qui: Univ. del Salento
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SVA: The Power of Assertions in SystemVerilog [[electronic resource] /] / by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
SVA: The Power of Assertions in SystemVerilog [[electronic resource] /] / by Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
Autore Cerny Eduard
Edizione [2nd ed. 2015.]
Pubbl/distr/stampa Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Descrizione fisica 1 online resource (589 p.)
Disciplina 004.1
621.381548
Soggetto topico Electronic circuits
Microprocessors
Circuits and Systems
Processor Architectures
Electronic Circuits and Devices
ISBN 3-319-07139-4
Formato Materiale a stampa
Livello bibliografico Monografia
Lingua di pubblicazione eng
Nota di contenuto Part I. Opening -- Introduction -- System Verilog Language and Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference.- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences.- Clocks -- Resets -- Procedural Concurrent Assertions.- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers -- Checkers in Formal Verification.- Checker Libraries -- Appendix -- References.- Index.
Record Nr. UNINA-9910299847903321
Cerny Eduard  
Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015
Materiale a stampa
Lo trovi qui: Univ. Federico II
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