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High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (XIII, 370 p.) |
| Disciplina | 005.4/53 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer programming
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Programming Techniques Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN |
1-280-38556-1
9786613563484 3-642-11515-2 |
| Formato | Materiale a stampa  |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. |
| Record Nr. | UNISA-996465510303316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell
| High Performance Embedded Architectures and Compilers [[electronic resource] ] : 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010, Proceedings / / edited by Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell |
| Edizione | [1st ed. 2010.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
| Descrizione fisica | 1 online resource (XIII, 370 p.) |
| Disciplina | 005.4/53 |
| Collana | Theoretical Computer Science and General Issues |
| Soggetto topico |
Computer programming
Computer arithmetic and logic units Microprocessors Computer architecture Computer input-output equipment Logic design Computer networks Programming Techniques Arithmetic and Logic Structures Processor Architectures Input/Output and Data Communications Logic Design Computer Communication Networks |
| ISBN |
1-280-38556-1
9786613563484 3-642-11515-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Invited Program -- Embedded Systems as Datacenters -- Larrabee: A Many-Core Intel Architecture for Visual Computing -- Architectural Support for Concurrency -- Remote Store Programming -- Low-Overhead, High-Speed Multi-core Barrier Synchronization -- Improving Performance by Reducing Aborts in Hardware Transactional Memory -- Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems -- Compilation and Runtime Systems -- Split Register Allocation: Linear Complexity Without the Performance Penalty -- Trace-Based Data Layout Optimizations for Multi-core Processors -- Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors -- Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures -- Reconfigurable and Customized Architectures -- Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions -- Accelerating XML Query Matching through Custom Stack Generation on FPGAs -- An Application-Aware Load Balancing Strategy for Network Processors -- Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays -- Multicore Efficiency, Reliability, and Power -- Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors -- Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors -- RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor -- Performance and Power Aware CMP Thread Allocation Modeling -- Memory Organization and Optimization -- Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching -- Scalable Shared-Cache Management by Containing Thrashing Workloads -- SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs -- DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems -- Programming and Analysis of Accelerators -- Tagged Procedure Calls (TPC): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor -- Analysis of Task Offloading for Accelerators -- Offload – Automating Code Migration to Heterogeneous Multicore Systems -- Computer Generation of Efficient Software Viterbi Decoders. |
| Record Nr. | UNINA-9910484851603321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas
| Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas |
| Autore | Campbell Bill |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 |
| Descrizione fisica | 1 online resource (378 pages) |
| Disciplina | 005.4/53 |
| Soggetto topico |
Compilers (Computer programs)
Java (Computer program language) |
| Soggetto genere / forma | Electronic books. |
| ISBN |
0-429-06774-7
1-4398-6088-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Compilation -- chapter 2 Lexical Analysis -- chapter 3 Parsing -- chapter 4 Type Checking -- chapter 5 JVM Code Generation -- chapter 6 Translating JVM Code to MIPS Code -- chapter 7 Register Allocation -- chapter 8 Celebrity Compilers. |
| Record Nr. | UNINA-9910465172003321 |
Campbell Bill
|
||
| Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas
| Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas |
| Autore | Campbell Bill |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 |
| Descrizione fisica | 1 online resource (378 pages) |
| Disciplina | 005.4/53 |
| Soggetto topico |
Compilers (Computer programs)
Java (Computer program language) |
| ISBN |
0-429-06774-7
1-4398-6088-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Compilation -- chapter 2 Lexical Analysis -- chapter 3 Parsing -- chapter 4 Type Checking -- chapter 5 JVM Code Generation -- chapter 6 Translating JVM Code to MIPS Code -- chapter 7 Register Allocation -- chapter 8 Celebrity Compilers. |
| Record Nr. | UNINA-9910792134603321 |
|
Campbell Bill
|
||
| Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas
| Introduction to compiler construction in a Java World / / by Bill Campbell, Swami Iyer and Bahar Akbal-Delibas |
| Autore | Campbell Bill |
| Edizione | [1st edition] |
| Pubbl/distr/stampa | Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 |
| Descrizione fisica | 1 online resource (378 pages) |
| Disciplina | 005.4/53 |
| Soggetto topico |
Compilers (Computer programs)
Java (Computer program language) |
| ISBN |
0-429-06774-7
1-4398-6088-2 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | chapter 1 Compilation -- chapter 2 Lexical Analysis -- chapter 3 Parsing -- chapter 4 Type Checking -- chapter 5 JVM Code Generation -- chapter 6 Translating JVM Code to MIPS Code -- chapter 7 Register Allocation -- chapter 8 Celebrity Compilers. |
| Record Nr. | UNINA-9910812938003321 |
|
Campbell Bill
|
||
| Boca Raton, FL : , : Chapman and Hall/CRC, an imprint of Taylor and Francis, , 2012 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Modular Compiler Verification [[electronic resource] ] : A Refinement-Algebraic Approach Advocating Stepwise Abstraction / / by Markus Müller-Olm
| Modular Compiler Verification [[electronic resource] ] : A Refinement-Algebraic Approach Advocating Stepwise Abstraction / / by Markus Müller-Olm |
| Autore | Müller-Olm Markus |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XVI, 260 p.) |
| Disciplina | 005.4/53 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Programming languages (Electronic computers)
Architecture, Computer Software engineering Computer logic Special purpose computers Programming Languages, Compilers, Interpreters Computer System Implementation Software Engineering Logics and Meanings of Programs Special Purpose and Application-Based Systems |
| ISBN | 3-540-69539-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Complete Boolean lattices -- Galois connections -- States, valuation functions and predicates -- The algebra of commands -- Communication and time -- Data refinement -- Transputer base model -- A small hard real-time programming language -- A hierarchy of views -- Compiling-correctness relations -- Translation theorems -- A functional implementation -- Conclusion. |
| Record Nr. | UNINA-9910144918103321 |
|
Müller-Olm Markus
|
||
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Modular Compiler Verification [[electronic resource] ] : A Refinement-Algebraic Approach Advocating Stepwise Abstraction / / by Markus Müller-Olm
| Modular Compiler Verification [[electronic resource] ] : A Refinement-Algebraic Approach Advocating Stepwise Abstraction / / by Markus Müller-Olm |
| Autore | Müller-Olm Markus |
| Edizione | [1st ed. 1997.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 |
| Descrizione fisica | 1 online resource (XVI, 260 p.) |
| Disciplina | 005.4/53 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Programming languages (Electronic computers)
Architecture, Computer Software engineering Computer logic Special purpose computers Programming Languages, Compilers, Interpreters Computer System Implementation Software Engineering Logics and Meanings of Programs Special Purpose and Application-Based Systems |
| ISBN | 3-540-69539-7 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Complete Boolean lattices -- Galois connections -- States, valuation functions and predicates -- The algebra of commands -- Communication and time -- Data refinement -- Transputer base model -- A small hard real-time programming language -- A hierarchy of views -- Compiling-correctness relations -- Translation theorems -- A functional implementation -- Conclusion. |
| Record Nr. | UNISA-996465760403316 |
|
Müller-Olm Markus
|
||
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1997 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Sixth annual Workshop on Interaction between Compilers and Computer Architectures : Cambridge, Massachusetts, 3 February 2002 : proceedings
| Sixth annual Workshop on Interaction between Compilers and Computer Architectures : Cambridge, Massachusetts, 3 February 2002 : proceedings |
| Pubbl/distr/stampa | [Place of publication not identified], : IEEE Computer Society, 2002 |
| Disciplina | 005.4/53 |
| Soggetto topico |
Compilers (Computer programs)
Computer architecture Engineering & Applied Sciences Computer Science |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Record Nr. | UNISA-996200682903316 |
| [Place of publication not identified], : IEEE Computer Society, 2002 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
Types in Compilation [[electronic resource] ] : Third International Workshop, TIC 2000, Montreal, Canada, September 21, 2000. Revised Selected Papers / / edited by Robert Harper
| Types in Compilation [[electronic resource] ] : Third International Workshop, TIC 2000, Montreal, Canada, September 21, 2000. Revised Selected Papers / / edited by Robert Harper |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (X, 214 p.) |
| Disciplina | 005.4/53 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Programming languages (Electronic computers)
Computer logic Mathematical logic Programming Languages, Compilers, Interpreters Logics and Meanings of Programs Mathematical Logic and Formal Languages |
| ISBN | 3-540-45332-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Types in Compilation -- Sound and Complete Elimination of Singleton Kinds -- Program Representation Size in an Intermediate Language with Intersection and Union Types -- An Abstract Model of Java Dynamic Linking and Loading -- Sharing in Typed Module Assembly Language -- Scalable Certification for Typed Assembly Language -- Safe and Flexible Dynamic Linking of Native Code -- Alias Types for Recursive Data Structures. |
| Record Nr. | UNINA-9910143602103321 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. Federico II | ||
| ||
Types in Compilation [[electronic resource] ] : Third International Workshop, TIC 2000, Montreal, Canada, September 21, 2000. Revised Selected Papers / / edited by Robert Harper
| Types in Compilation [[electronic resource] ] : Third International Workshop, TIC 2000, Montreal, Canada, September 21, 2000. Revised Selected Papers / / edited by Robert Harper |
| Edizione | [1st ed. 2001.] |
| Pubbl/distr/stampa | Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 |
| Descrizione fisica | 1 online resource (X, 214 p.) |
| Disciplina | 005.4/53 |
| Collana | Lecture Notes in Computer Science |
| Soggetto topico |
Programming languages (Electronic computers)
Computer logic Mathematical logic Programming Languages, Compilers, Interpreters Logics and Meanings of Programs Mathematical Logic and Formal Languages |
| ISBN | 3-540-45332-6 |
| Formato | Materiale a stampa |
| Livello bibliografico | Monografia |
| Lingua di pubblicazione | eng |
| Nota di contenuto | Types in Compilation -- Sound and Complete Elimination of Singleton Kinds -- Program Representation Size in an Intermediate Language with Intersection and Union Types -- An Abstract Model of Java Dynamic Linking and Loading -- Sharing in Typed Module Assembly Language -- Scalable Certification for Typed Assembly Language -- Safe and Flexible Dynamic Linking of Native Code -- Alias Types for Recursive Data Structures. |
| Record Nr. | UNISA-996465908003316 |
| Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2001 | ||
| Materiale a stampa | ||
| Lo trovi qui: Univ. di Salerno | ||
| ||
