1990 proceedings

• Pubblicazione: [Place of publication not identified], : IEEE Computer Society Press, 1990
• Descrizione fisica: 1 online resource (xiv, 342 pages) : illustrations
• Disciplina: 621.3815
• Soggetto topico: Integrated circuits - Wafer-scale integration
• Note generali: Bibliographic Level Mode of Issuance: Monograph
• Nota di contenuto: The Lincoln programmable image-processing wafer,"R. -- MUSE: a wafer-scale systolic DSP,"D. -- WASP: a wafer-scale massively parallel processor,"R. -- The WASP demonstrator programme: the engineering of a wafer-scale system,"I. -- Re-wafer scale integration: a new approach to active phased arrays,"L. -- A 64 Mb MROM with good pair selection architecture,"K. -- A high performance single chip FFT array processor for wafer scale integration,"Jaehee -- Implementation of configurable hardware using wafer scale integration,"T. -- Crosspoint Arithmetic Processor architecture for wafer scale integration,"J. -- A linear-array WSI architecture for improved yield and performance,"R. -- Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration,"P. -- WSI architecture for L-U decomposition: a radar array processor,"V. -- Defect tolerance scheme for gigaFLOP WSI architectures,"A. -- A general configurable architecture for WSI implementation for neural nets,"F. -- WSI architecture of a neurocomputer module,"U. -- Defect tolerant sorting networks for WSI implementation,"Sheng-Chiech -- Data manipulator network for WSI designs,"J. -- Multiple fault detection and location in WSI baseline interconnection networks,"C. -- Effects of switch failure on soft-configurable WSI yield,"M. -- Defect tolerant implementations of feed-forward and recurrent neural networks," -- A visually oriented architectural fault simulation environment for WSI," -- Hierarchical fault tolerance for 3D microelectronics," -- Distributed diagnosis for wafer scale systems," -- Fault tolerance performance of WSI systolic sorter," -- Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units," -- A defect and fault tolerant design of WSI static RAM modules, -- A methodology for wafer scale integration of linear pipelined arrays," -- Some new algorithms for reconfiguring VLSI/WSI arrays," -- Soft-programmable bypass switch design for defect-tolerant arrays," -- Yield enhancement for WSI array processors using two-and-half-track switches," -- Testing wafer scale arrays: constant testability under multiple faults," -- A self-test methodology for restructurable WSI," -- Divide-and-conquer in wafer scale array testing," -- Yield modeling and optimization of large redundant RAMs," -- Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits," -- Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations," -- Hybrid wafer scale interconnection inventing a new technology," -- WSI implemented with button board interconnection," -- A study of high density multilayer LSI," -- Wafer scale integration (WSI) of programmable gate arrays (PGA's),". --.
• Titolo autorizzato: 1990 proceedings
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 996211381703316
• Lo trovi qui: Univ. di Salerno