System Level Design from HW/SW to Memory for Embedded Systems : 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3–6, 2015, Proceedings / / edited by Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg

• Pubblicazione: Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017
• Edizione: 1st ed. 2017.
• Descrizione fisica: 1 online resource (XII, 231 p. 92 illus.)
• Disciplina: 004.16
• Soggetto topico: Computers, Special purpose; Computers; Computer systems; Software engineering; Special Purpose and Application-Based Systems; Computer Hardware; Computer System Implementation; Software Engineering
• Persona (resp. second.): GötzMarcelo; SchirnerGunar; WehrmeisterMarco Aurélio; Al FaruqueMohammad Abdullah; RettbergAchim
• Note generali: Includes index.
• Sommario/riassunto: This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.
• Titolo autorizzato: System Level Design from HW
• ISBN: 3-319-90023-4
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 9910280950703321
• Lo trovi qui: Univ. Federico II
• Serie: IFIP Advances in Information and Communication Technology, . 1868-422X ; ; 523