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Titolo: | Hardware and Software: Verification and Testing [[electronic resource] ] : 10th International Haifa Verification Conference, HVC 2014, Haifa, Israel, November 18-20, 2014, Proceedings / / edited by Eran Yahav |
Pubblicazione: | Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 |
Edizione: | 1st ed. 2014. |
Descrizione fisica: | 1 online resource (XVI, 302 p. 78 illus.) |
Disciplina: | 005.14 |
Soggetto topico: | Software engineering |
Computer logic | |
Programming languages (Electronic computers) | |
Artificial intelligence | |
Mathematical logic | |
Computer communication systems | |
Software Engineering | |
Logics and Meanings of Programs | |
Programming Languages, Compilers, Interpreters | |
Artificial Intelligence | |
Mathematical Logic and Formal Languages | |
Computer Communication Networks | |
Persona (resp. second.): | YahavEran |
Note generali: | Bibliographic Level Mode of Issuance: Monograph |
Nota di contenuto: | Using Coarse-Grained Abstractions to Verify Linearizability on TSO Architectures -- Enhancing Scenario Quality Using Quasi-Events -- Combined Bounded and Symbolic Model Checking for Incomplete Timed Systems -- DynaMate: Dynamically Inferring Loop Invariants for Automatic Full Functional Verification -- Generating Modulo-2 Linear Invariants for Hardware Model Checking -- Suraq — A Controller Synthesis Tool Using Uninterpreted Functions -- Synthesizing Finite-State Protocols from Scenarios and Requirements -- Automatic Error Localization for Software Using Deductive Verification -- Generating JML Specifications from Alloy Expressions -- Assume-Guarantee Abstraction Refinement Meets Hybrid Systems -- Handling TSO in Mechanized Linearizability Proofs -- Partial Quantifier Elimination -- Formal Verification of 800 Genetically Constructed Automata Programs: A Case Study -- A Framework to Synergize Partial Order Reduction with State Interpolation -- Reduction of Resolution Refutations and Interpolants via Subsumption -- Read, Write and Copy Dependencies for Symbolic Model Checking -- Efficient Combinatorial Test Generation Based on Multivalued Decision Diagrams -- Formal Verification of Secure User Mode Device Execution with DMA -- Supervisory Control of Discrete-Event Systems via IC3 -- Partial-Order Reduction for Multi-core LTL Model Checking -- A Comparative Study of Incremental Constraint Solving Approaches in Symbolic Execution. |
Sommario/riassunto: | This book constitutes the refereed proceedings of the 10th International Haifa Verification Conference, HVC 2014, held in Haifa, Israel, in November 2014. The 17 revised full papers and 4 short papers presented were carefully reviewed and selected from 43 submissions. The papers cover a wide range of topics in the sub-fields of testing and verification applicable to software, hardware, and complex hybrid systems. |
Titolo autorizzato: | Hardware and Software, Verification and Testing |
ISBN: | 3-319-13338-1 |
Formato: | Materiale a stampa |
Livello bibliografico | Monografia |
Lingua di pubblicazione: | Inglese |
Record Nr.: | 996210523003316 |
Lo trovi qui: | Univ. di Salerno |
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