IEC 62530 Edition 2.0 2011-05 IEEE Std 1800 : SystemVerilog : unified hardware design, specification, and verification language / / Institute of Electrical and Electronics Engineers

• Pubblicazione: Piscataway, New Jersey : , : IEEE, , 2011
• Descrizione fisica: 1 online resource (1294 pages)
• Disciplina: 621.392
• Soggetto topico: Verilog (Computer hardware description language); Computer hardware description languages
• Sommario/riassunto: This standard represents a merger of two previous standards: IEEE Std 1364™-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document.
• Altri titoli varianti: IEC 62530 Edition 2.0 2011-05 IEEE Std 1800: SystemVerilog Unified Hardware Design, Specification, and Verification Language
• Titolo autorizzato: IEC 62530 Edition 2.0 2011-05 IEEE Std 1800
• ISBN: 0-7381-6607-3
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Lingua di pubblicazione: Inglese
• Record Nr.: 9910135406503321
• Lo trovi qui: Univ. Federico II