{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":37,"n_cols":5,"rows_kept":37,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[13,2,13,3],[14,2,14,3],[15,2,15,3],[16,2,16,3],[17,2,17,3],[20,2,20,3],[21,2,21,3],[25,2,25,3],[27,2,27,3],[27,4,27,5],[28,2,28,3],[28,4,28,5],[29,2,29,3],[29,4,29,5],[30,2,30,3],[31,2,31,3],[32,2,32,3],[33,2,33,3],[34,2,34,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910822030103321"]
[null,null,"Autore",null,"Chu Pong P. <1959->"]
[null,null,"Titolo",null,"Embedded SoPC design with NIOS II processor and Verilog examples / / Pong P. Chu"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, N.J., : Wiley, c2012"]
[null,null,"ISBN",null,"9786613622228"]
[{"$nulls":4},"9781280592393"]
[{"$nulls":4},"1280592397"]
[{"$nulls":4},"9781118309575"]
[{"$nulls":4},"111830957X"]
[{"$nulls":4},"9781118309728"]
[{"$nulls":4},"1118309723"]
[{"$nulls":4},"9781118309469"]
[{"$nulls":4},"1118309464"]
[null,null,"Edizione",null,"[1st edition]"]
[null,null,"Descrizione fisica",null,"1 online resource (783 p.)"]
[null,null,"Classificazione",null,"TEC008010"]
[null,null,"Disciplina",null,"006.2/2"]
[null,null,"Soggetti",null,"Embedded computer systems"]
[{"$nulls":4},"Field programmable gate arrays"]
[{"$nulls":4},"Verilog (Computer hardware description language)"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"pt. I. Basic digital circuits development -- pt. II. Basic NIOS II software development -- pt. III. Custom I/O peripheral development -- pt. IV. Hardware accelerator case studies."]
[null,null,null,"Sommario/riassunto","\"This book explores the unique hardware programmability of FPGA (field-programmable gate array)-based embedded systems, using a learning-by-doing approach to introduce the concepts and techniques for embedded SoPC (system on a programmable chip) systems with Verilog. The book contains a large number of practical examples to illustrate and reinforce the hardware and software design concepts and techniques, as well as a complete code listing and experiment problems. The book is designed for upper-level undergraduate and entry-level graduate students in computer engineering, as well as practicing engineers\"--"]
[null,"2.","Record Nr.",null,"UNISANNIOCFIE039625"]
[null,null,"Autore",null,"Soave, Francesco"]
[null,null,"Titolo",null,"1: Istituzioni di logica di Francesco Soave ch. reg. som. regio professore parte prima"]
[null,null,"Pubbl/distr/stampa",null,"Venezia, : presso Andrea Santini, e figlio, 1801"]
[null,null,"Descrizione fisica",null,"216 p"]
[null,null,"Collocazione",null,"DEMARCO   FONDO RARI              A 130"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Segn.: A-I¹²."]