{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":16,"n_cols":5,"rows_kept":16,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[10,2,10,3],[11,2,11,3],[13,2,13,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISALENTO991003243699707536"]
[null,null,"Titolo",null,"Network processor design. Vol. 2, Issues and practices [electronic resource] / edited by Mark A. Franklin ... [et al.]."]
[null,null,"Pubbl/distr/stampa",null,"San Diego, Calif. ; London : Academic, 2003"]
[null,null,"ISBN",null,"9780121981570"]
[{"$nulls":4},"0121981576"]
[null,null,"Descrizione fisica",null,"384 p."]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Network processors - Design"]
[{"$nulls":4},"Application specific integrated circuits - Design"]
[{"$nulls":4},"Electronic books."]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Risorsa elettronica"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Network Processor Design: Issues and Practics, Volume 2 -- Contents -- Preface -- Chapter 1. Network Processors: Themes and Challenges, Patrick Crowley, Mark Franklin, Haldun Hadimioglu, and Peter Z. Onufryk -- Part 1. Design Principles -- Chapter 2. A Programmable Scalable Platform for Next Generation Networking, Christos J.Georgiou, Valentina Salapura, and Monty Denneau -- Chapter 3. Power Considerations in Network Processor Design, Mark A. Franklin and Tilman Wolf -- Chapter 4. Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors, Patrick Crowley and Jean-Loup Baer -- Chapter 5. Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas, Anand Srinivasan, Philip Holman, James Anderson, Sanjoy Baruah and Jasleen Kaur -- Chapter 6. A Massively Multithreaded Packet Processor, Steve Melvin, Mario Nemirovsky, Enric Musoll, Jeff Huynh, Rodolfo Milito, Hector Urdaneta, and Koroush Saraf -- Chapter 7. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors, Matthias Gries, Chidamber Kulkarni, Christian Sauer and Kurt Keutzer -- Chapter 8. Packet Classification and Termination in a Protocol Processor, Ulf Nordqvist and Dake Liu -- Chapter 9. NP-Click: A Programming Model for the Intel IXP1200, Niraj Shah, William Plishker and Kurt Keutzer -- Chapter 10. NEPAL: A Framework for Efficiently Structuring Applications for Network Processors, Gokhan Memik and William H. Mangione-Smith -- Chapter 11. Efficient and "]
[{"$nulls":4},"Faithful Performance Modeling for Network-Processor Based System Designs, Prashant Pradhan, Wen Xu, Indira Nair and Sambit Sahu -- Chapter 12. High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200, Roshan K. Thomas, Brian Mark, Tommy Johnson and James Croall -- Chapter 13. Directions in Packet Classification for Network Processors, Michael E. Kounavis, Alok Kumar, Harrick Vin, Raj Yavatkar and Andrew T. Campbell -- Part 2. Practices -- Chapter 14. Implementing High-performance, High-value Traffic Management Using Agere Network Processor Solutions, Jian-Guo Chen, David Sonnier, Robert Munoz, Vinoj Kumar, and Ambalavanar Arulambalam -- Chapter 15. AMCC - nPcoreTM \"NISC\" Architecture, Robin Melnick and Keith Morris -- Chapter 16. Adaptable Badwidth Allocation for QoS Support in Network Processors, Clark Jeffries, Mohammad Peyravian, and Ravi Sabhikhi -- Chapter 17. IDT - Network Search Engine with QDRTM LA-1 Interface, Michael J. Miller -- Chapter 18. Implementing Voice over AAL2 on a Network Processor, Jaroslaw Sydir, Prashant Chandra, Alok Kumar, Sridhar Lakshmanamurthy, Longsong Lin, Muthaiah Venkatachalam -- Chapter 19. Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor, Pranav Gambhire -- Chapter 20. A C-based Programming Language for Multiprocessor Network SoC Architectures. Kevin Crozier."]
[null,null,null,"Sommario/riassunto","Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors. Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service. Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linḵpings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington. Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum."]