{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":31,"n_cols":5,"rows_kept":31,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[23,2,23,3],[24,2,24,3],[28,2,28,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA996466116403316"]
[null,null,"Titolo",null,"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation [[electronic resource] ] : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings / / edited by Johan Vounckx, Nadine Azemard, Philippe Maurine"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006"]
[null,null,"ISBN",null,"3-540-39097-9"]
[null,null,"Edizione",null,"[1st ed. 2006.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XVI, 677 p.)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 4148"]
[null,null,"Classificazione",null,"SS 4800"]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Computer science"]
[{"$nulls":4},"Logic design"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Electronic digital computers—Evaluation"]
[{"$nulls":4},"Computer arithmetic and logic units"]
[{"$nulls":4},"Computer storage devices"]
[{"$nulls":4},"Memory management (Computer science)"]
[{"$nulls":4},"Theory of Computation"]
[{"$nulls":4},"Logic Design"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"System Performance and Evaluation"]
[{"$nulls":4},"Arithmetic and Logic Structures"]
[{"$nulls":4},"Computer Memory Structure"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Session 1 – High-Level Design -- Session 2 – Power Estimation / Modeling -- Session 3 – Memory and Register Files -- Session 4 – Low-Power Digital Circuits -- Session 5 – Busses and Interconnects -- Session 6 – Low Power Techniques -- Session 7 – Applications and SoC Design -- Session 8 – Modeling -- Session 9 – Digital Circuits -- Session 10 – Reconfigurable and Programmable Devices -- Poster 1 -- Poster 2 -- Poster 3 -- Keynotes -- Industrial Session."]
[null,null,null,"Sommario/riassunto","Welcome to the proceedings of PATMOS 2006, the 16th in a series of "]
[{"$nulls":4},"international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript."]