{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":29,"n_cols":5,"rows_kept":29,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[22,2,22,3],[23,2,23,3],[26,2,26,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA996466040903316"]
[null,null,"Autore",null,"Müller Silvia M"]
[null,null,"Titolo",null,"The Complexity of Simple Computer Architectures [[electronic resource] /] / edited by Silvia M. Müller, Wolfgang J. Paul"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1995"]
[null,null,"ISBN",null,"3-540-47774-8"]
[null,null,"Edizione",null,"[1st ed. 1995.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XII, 273 p.)"]
[null,null,"Collana",null,"Lecture Notes in Computer Science, , 0302-9743 ; ; 995"]
[null,null,"Disciplina",null,"004.2/2"]
[null,null,"Soggetti",null,"Microprogramming "]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer system failures"]
[{"$nulls":4},"Arithmetic and logic units, Computer"]
[{"$nulls":4},"Electronics"]
[{"$nulls":4},"Microelectronics"]
[{"$nulls":4},"Logic design"]
[{"$nulls":4},"Control Structures and Microprogramming"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"System Performance and Evaluation"]
[{"$nulls":4},"Arithmetic and Logic Structures"]
[{"$nulls":4},"Electronics and Microelectronics, Instrumentation"]
[{"$nulls":4},"Logic Design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,"Nota di contenuto",null,"The formal architecture model -- Functional modules -- Hardwired control -- Design of a minimal CPU -- Design of the DLX machine -- Trade-off analyses -- Interrupt -- Microprogrammed control -- Further applications of the architecture model."]
[null,null,null,"Sommario/riassunto","This book presents a formal model for evaluating the cost effectiveness of computer architectures. The model can cope with a wide range of architectures, from CPU design to parallel supercomputers. To illustrate the formal procedure of trade-off analyses, several non-pipelined design alternatives for the well-known RISC architecture called DLX are analyzed quantitatively. It is formally proved that the interrupt mechanism proposed for the DLX architecture handles nested interrupts correctly. In an appendix all programs to compute the cost "]
[{"$nulls":4},"and cycle time of the designs described are listed in C code. Running these simple C programs on a PC is sufficient to verify the results presented. The book addresses design professionals and students in computer architecture."]