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[null,null,"Titolo",null,"Correct Hardware Design and Verification Methods [[electronic resource] ] : 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings / / edited by Dominique Borrione, Wolfgang Paul"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005"]
[null,null,"Edizione",null,"[1st ed. 2005.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XII, 414 p.)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 3725"]
[null,null,"Disciplina",null,"621.39/5"]
[null,null,"Soggetti",null,"Computer science"]
[{"$nulls":4},"Computers"]
[{"$nulls":4},"Software engineering"]
[{"$nulls":4},"Machine theory"]
[{"$nulls":4},"Artificial intelligence"]
[{"$nulls":4},"Theory of Computation"]
[{"$nulls":4},"Computer Hardware"]
[{"$nulls":4},"Computer Science Logic and Foundations of Programming"]
[{"$nulls":4},"Software Engineering"]
[{"$nulls":4},"Formal Languages and Automata Theory"]
[{"$nulls":4},"Artificial Intelligence"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic "]
[{"$nulls":4},"Scheduling, Don’t Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties."]