{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":27,"n_cols":5,"rows_kept":27,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[20,2,20,3],[21,2,21,3],[25,2,25,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA996465790003316"]
[null,null,"Titolo",null,"Correct Hardware Design and Verification Methods [[electronic resource] ] : 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings / / edited by Daniel Geist, Enrico Tronci"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003"]
[null,null,"ISBN",null,"3-540-39724-8"]
[null,null,"Edizione",null,"[1st ed. 2003.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XII, 432 p.)"]
[null,null,"Collana",null,"Lecture Notes in Computer Science, , 0302-9743 ; ; 2860"]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Computers"]
[{"$nulls":4},"Computer hardware"]
[{"$nulls":4},"Computer logic"]
[{"$nulls":4},"Software engineering"]
[{"$nulls":4},"Mathematical logic"]
[{"$nulls":4},"Artificial intelligence"]
[{"$nulls":4},"Theory of Computation"]
[{"$nulls":4},"Computer Hardware"]
[{"$nulls":4},"Logics and Meanings of Programs"]
[{"$nulls":4},"Software Engineering"]
[{"$nulls":4},"Mathematical Logic and Formal Languages"]
[{"$nulls":4},"Artificial Intelligence"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Invited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based "]
[{"$nulls":4},"Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- “More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques."]