{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":37,"n_cols":5,"rows_kept":37,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[20,2,20,3],[21,2,21,3],[25,2,25,3],[28,2,28,3],[28,4,28,5],[29,2,29,3],[29,4,29,5],[30,2,30,3],[30,4,30,5],[31,2,31,3],[32,2,32,3],[33,2,33,3],[34,2,34,3],[35,2,35,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA996465559003316"]
[null,null,"Titolo",null,"Formal Methods in Computer-Aided Design [[electronic resource] ] : 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings / / edited by Mark D. Aagaard, John W. O'Leary"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2002"]
[null,null,"ISBN",null,"3-540-36126-X"]
[null,null,"Edizione",null,"[1st ed. 2002.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XII, 408 p.)"]
[null,null,"Collana",null,"Lecture Notes in Computer Science, , 0302-9743 ; ; 2517"]
[null,null,"Disciplina",null,"621.39/2"]
[null,null,"Soggetti",null,"Computer-aided engineering"]
[{"$nulls":4},"Computer hardware"]
[{"$nulls":4},"Software engineering"]
[{"$nulls":4},"Computer logic"]
[{"$nulls":4},"Mathematical logic"]
[{"$nulls":4},"Electrical engineering"]
[{"$nulls":4},"Computer-Aided Engineering (CAD, CAE) and Design"]
[{"$nulls":4},"Computer Hardware"]
[{"$nulls":4},"Software Engineering"]
[{"$nulls":4},"Logics and Meanings of Programs"]
[{"$nulls":4},"Mathematical Logic and Formal Languages"]
[{"$nulls":4},"Electrical Engineering"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Abstraction -- Abstraction by Symbolic Indexing Transformations -- Counter-Example Based Predicate Discovery in Predicate Abstraction -- Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis -- Symbolic Simulation -- Simplifying Circuits for Formal Verification Using Parametric Representation -- Generalized Symbolic Trajectory Evaluation — Abstraction in Action -- Model Checking: Strongly-Connected Components -- Analysis of Symbolic SCC Hull Algorithms -- Sharp Disjunctive Decomposition for Language Emptiness Checking -- Microprocessor Specification and Verification -- Relating Multi-step and Single-Step Microprocessor Correctness Statements -- Modeling and Verification of Out-of-Order Microprocessors in UCLID -- Decision "]
[{"$nulls":4},"Procedures -- On Solving Presburger and Linear Arithmetic with SAT -- Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods -- Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers -- Model Checking: Reachability Analysis -- Exploiting Transition Locality in the Disk Based Mur? Verifier -- Traversal Techniques for Concurrent Systems -- Model Checking: Fixed Points -- A Fixpoint Based Encoding for Bounded Model Checking -- Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths -- Verification Techniques and Methodology -- Mechanical Verification of a Square Root Algorithm Using Taylor’s Theorem -- A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols -- Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV -- Hardware Description Languages -- Functional Design Using Behavioural and Structural Components -- Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries -- Prototyping and Synthesis -- Input/Output Compatibility of Reactive Systems -- Smart Play-out of Behavioral Requirements."]
[null,null,null,"Sommario/riassunto","This volume contains the proceedings of the Fourth Biennial Conference on F- mal Methods in Computer-Aided Design (FMCAD). The conference is devoted to the use of mathematical methods for the analysis of digital hardware c- cuits and systems. The workreported in this bookdescribes the use of formal mathematics and associated tools to design and verify digital hardware systems. Functional veri?cation has become one of the principal costs in a modern computer design e?ort. FMCAD provides a venue for academic and industrial researchers and practitioners to share their ideas and experiences of using - screte mathematical modeling and veri?cation. Over the past 20 years, this area has grown from just a few academic researchers to a vibrant worldwide com- nity of people from both academia and industry. This volume includes 23 papers selected from the 47 submitted papers, each of which was reviewed by at least three program committee members. The history of FMCAD dates backto 1984, when the earliest meetings on this topic occurred as part of IFIP WG10.2."]
[null,"2.","Record Nr.",null,"UNICAMPANIAVAN00092540"]
[null,null,"Autore",null,"Miscali, Mario"]
[null,null,"Titolo",null,"Il diritto alla giusta imposta : contributo allo studio del diritto all'equa redistribuzione delle risorse /   Mario Miscali"]
[null,null,"Pubbl/distr/stampa",null,"Milano, : Pearson, 2009"]
[null,null,"ISBN",null,"978-88-7192-581-3"]
[null,null,"Descrizione fisica",null,"X, 166 p. : 24 cm."]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]