{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":3,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":49,"n_cols":5,"rows_kept":49,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[11,2,11,3],[11,4,11,5],[12,2,12,3],[12,4,12,5],[13,2,13,3],[13,4,13,5],[14,2,14,3],[15,2,15,3],[16,2,16,3],[18,2,18,3],[19,2,19,3],[25,2,25,3],[25,4,25,5],[26,2,26,3],[26,4,26,5],[27,2,27,3],[27,4,27,5],[28,2,28,3],[30,2,30,3],[35,2,35,3],[36,2,36,3],[37,2,37,3],[39,2,39,3],[41,2,41,3],[42,2,42,3],[46,2,46,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA990006162130403321"]
[null,null,"Autore",null,"Balsano, Ferdinando"]
[null,null,"Titolo",null,"Delle dottrine filosofiche e civili ... : con saggio sulla opere del Gravina pel Prof. Vincenzo Julia / Ferdinando Balsano"]
[null,null,"Pubbl/distr/stampa",null,"Cosenza : Tip. Migliaccio, 1879"]
[null,null,"Descrizione fisica",null,"410 p. ; 20 cm"]
[null,null,"Disciplina",null,"340.1"]
[null,null,"Locazione",null,"FGBC"]
[null,null,"Collocazione",null,"XI C 206"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,"2.","Record Nr.",null,"UNISA996387824103316"]
[null,null,"Autore",null,"Davies Joseph"]
[null,null,"Titolo",null,"An humble proposal that may intirely check and restrain, the growth of highway-men, foot-pads, house-breakers, shop-lifters and other incendiary's, by threatening letters; [[electronic resource] ] : and at no charge to the government, but in case of a war, may be an hundred thousand a year, in the way of trade of this kingdom. / / By Joseph Davies"]
[null,null,"Pubbl/distr/stampa",null,"London : , : Printed, by L. How, in Petticoat-Lane., [ca. 1690]"]
[null,null,"Descrizione fisica",null,"8 p"]
[null,null,"Soggetti",null,"Galleys - Great Britain"]
[{"$nulls":4},"Crime prevention - Great Britain"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Date of publication suggested by Wing."]
[{"$nulls":4},"Wing (2nd ed.) attributes to Joseph Davis."]
[{"$nulls":4},"Reproduction of original in the University of Illinois (Urbana-Champaign Campus). Library."]
[null,null,null,"Sommario/riassunto","eebo-0167"]
[null,"3.","Record Nr.",null,"UNINA9910829918003321"]
[null,null,"Autore",null,"Chu Pong P. <1959->"]
[null,null,"Titolo",null,"RTL hardware design using VHDL : coding for efficiency, portability, and scalability / / Pong P. Chu"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, New Jersey : , : Wiley-Interscience, , c2006"]
[{"$nulls":4},"[Piscataqay, New Jersey] : , : IEEE Xplore, , [2006]"]
[null,null,"ISBN",null,"1-280-44810-5"]
[{"$nulls":4},"9786610448104"]
[{"$nulls":4},"0-470-32489-9"]
[{"$nulls":4},"0-471-78641-1"]
[{"$nulls":4},"0-471-78639-X"]
[null,null,"Edizione",null,"[[First edition].]"]
[null,null,"Descrizione fisica",null,"1 online resource (695 p.)"]
[null,null,"Disciplina",null,"621.39/2"]
[{"$nulls":4},"621.392"]
[null,null,"Soggetti",null,"Digital electronics - Data processing"]
[{"$nulls":4},"VHDL (Computer hardware description language)"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references (p. 665-666) and index."]
[null,null,"Nota di contenuto",null,"Introduction to digital system design -- Overview of hardware description languages -- Basic language constructs of VHDL -- Concurrent signal assignment statements of VHDL -- Sequential statements of VHDL -- Synthesis of VHDL code -- Combinational circuit design : practice -- Sequential circuit design : principle -- Sequential circuit design : practice -- Finite state machine : principle and practice -- Register transfer methodology : principle -- Register transfer methodology : practice -- Hierarchical design in VHDL -- Parameterized design : principle -- Parameterized design : practice -- Clock and synchronization : principle and practice."]
[null,null,null,"Sommario/riassunto","The skills and guidance needed to master RTL hardware design This book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software. Focusing on the module-level design, which is composed of functional units, routing circuit, and storage, the book illustrates the relationship between the VHDL constructs and the underlying hardware components, and shows how to develop codes that faithfully reflect the "]
[{"$nulls":4},"module-level design and can be synthesized into efficient gate-level implementation. Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains Although the focus of the book is RTL synthesis, it also examines the synthesis task from the perspective of the overall development process. Readers learn good design practices and guidelines to ensure that an RTL design can accommodate future simulation, verification, and testing needs, and can be easily incorporated into a larger system or reused. Discussion is independent of technology and can be applied to both ASIC and FPGA devices. With a balanced presentation of fundamentals and practical examples, this is an excellent textbook for upper-level undergraduate or graduate courses in advanced digital logic. Engineers who need to make effective use of today's synthesis software and FPGA devices should also refer to this book."]