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[null,"1.","Record Nr.",null,"UNISA990006152660203316"]
[null,null,"Autore",null,"WEBER, Max <1864-1920>"]
[null,null,"Titolo",null,"5.: I fondamenti razionali e sociologici della musica / Max Weber ; introduzione di Pietro Rossi"]
[null,null,"Pubbl/distr/stampa",null,"Milano : Edizioni di Comunità, 1980"]
[null,null,"Descrizione fisica",null,"V, 87 p. ; 20 cm"]
[null,null,"Collana",null,"Classici della sociologia"]
[null,null,"Disciplina",null,"306.484"]
[null,null,"Soggetti",null,"Musica - Sociologia"]
[null,null,"Collocazione",null,"XVI.5. 591/5"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Titolo in copertina"]
[null,"2.","Record Nr.",null,"UNINA9911006627103321"]
[null,null,"Autore",null,"Pasricha Sudeep"]
[null,null,"Titolo",null,"On-chip communication architectures : system on chip interconnect / / Sudeep Pasricha, Nikil Dutt"]
[null,null,"Pubbl/distr/stampa",null,"Amsterdam ; ; Boston, : Elsevier / Morgan Kaufmann Publishers, c2008"]
[null,null,"ISBN",null,"9786611370947"]
[{"$nulls":4},"9781281370945"]
[{"$nulls":4},"1281370940"]
[{"$nulls":4},"9780080558288"]
[{"$nulls":4},"0080558283"]
[null,null,"Edizione",null,"[1st edition]"]
[null,null,"Descrizione fisica",null,"1 online resource (541 p.)"]
[null,null,"Collana",null,"Systems on Silicon"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Systems on a chip"]
[{"$nulls":4},"Microcomputers - Buses"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Interconnects (Integrated circuit technology)"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Front Cover; On-Chip Communication Architectures: System on Chip Interconnect; Copyright Page; Contents; Preface; About the Authors; Acknowledgments; List of Contributors; CHAPTER 1 Introduction; 1.1. Trends in System-On-Chip Design; 1.2. Coping with Soc Design Complexity; 1.3. ESL Design Flow; 1.4. On-Chip Communication Architectures: A Quick Look; 1.5. Book Outline; CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures; 2.1. Terminology; 2.2. Characteristics of Bus-Based Communication Architectures; 2.3. Data Transfer Modes; 2.4. Bus Topology Types"]
[{"$nulls":4},"2.5. Physical Implementation of Bus Wires2.6. Discussion: Buses in the DSM Era; 2.7. Summary; CHAPTER 3 On-Chip Communication Architecture Standards; 3.1. Standard On-Chip Bus-Based Communication Architectures; 3.2. Socket-Based On-Chip Bus Interface Standards; 3.3. Discussion: Off-Chip Bus Architecture Standards; 3.4. Summary; CHAPTER 4 Models for Performance Exploration; 4.1. Static Performance Estimation Models; 4.2. Dynamic (Simulation-Based) Performance Estimation Models; 4.3. Hybrid Communication Architecture Performance Estimation Approaches; 4.4. Summary"]
[{"$nulls":4},"CHAPTER 5 Models for Power and Thermal Estimation5.1. Bus Wire "]
[{"$nulls":4},"Power Models; 5.2. Comprehensive Bus Architecture Power Models; 5.3. Bus Wire Thermal Models; 5.4. Discussion: PVT Variation-Aware Power Estimation; 5.5. Summary; CHAPTER 6 Synthesis of On-Chip Communication Architectures; 6.1. Bus Topology Synthesis; 6.2. Bus Protocol Parameter Synthesis; 6.3. Bus Topology and Protocol Parameter Synthesis; 6.4. Physical Implementation Aware Synthesis; 6.5. Memory-Communication Architecture Co-synthesis; 6.6. Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures"]
[{"$nulls":4},"6.7. SummaryCHAPTER 7 Encoding Techniques for On-Chip Communication Architectures; 7.1. Techniques for Power Reduction; 7.2. Techniques for Reducing Capacitive Crosstalk Delay; 7.3. Techniques for Reducing Power and Capacitive Crosstalk Effects; 7.4. Techniques for Reducing Inductive Crosstalk Effects; 7.5. Techniques for Fault Tolerance and Reliability; 7.6. Summary; CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design; 8.1. Split Bus Architectures; 8.2. Serial Bus Architectures; 8.3. CDMA-Based Bus Architectures; 8.4. Asynchronous Bus Architectures"]
[{"$nulls":4},"8.5. Dynamically Reconfigurable Bus Architectures8.6. Summary; CHAPTER 9 On-Chip Communication Architecture Refinement and Interface Synthesis; 9.1. On-Chip Communication Architecture Refinement; 9.2. Interface Synthesis; 9.3. Discussion: Interface Synthesis; 9.4. Summary; CHAPTER 10 Verification and Security Issues in On-Chip Communication Architecture Design; 10.1. Verification of On-Chip Communication Protocols; 10.2. Compliance Verification for IP Block Integration; 10.3. Basic Concepts of SoC Security; 10.4. Security Support in Standard Bus Protocols"]
[{"$nulls":4},"10.5. Communication Architecture Enhancements for Improving SoC Security"]
[null,null,null,"Sommario/riassunto","Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip.  New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs.  As application complexity strains"]