{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":35,"n_cols":5,"rows_kept":35,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[10,2,10,3],[11,2,11,3],[13,2,13,3],[13,4,13,5],[14,2,14,3],[14,4,14,5],[15,2,15,3],[15,4,15,5],[16,2,16,3],[18,2,18,3],[20,2,20,3],[21,2,21,3],[22,2,22,3],[24,2,24,3],[25,2,25,3],[28,2,28,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA990000447600203316"]
[null,null,"Autore",null,"LARSON, Ronald G."]
[null,null,"Titolo",null,"The  structure and rheology of complex fluids / Ronald G. Larson"]
[null,null,"Pubbl/distr/stampa",null,"New York ; Oxford : Oxford University press, 1999"]
[null,null,"ISBN",null,"0-19-512197-X"]
[null,null,"Descrizione fisica",null,"XXI, 663 p. : ill. ; 24 cm"]
[null,null,"Collana",null,"Topics in chemical engineering"]
[null,null,"Disciplina",null,"530.42"]
[null,null,"Soggetti",null,"Reologia"]
[null,null,"Collocazione",null,"530.42 LAR"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,"2.","Record Nr.",null,"UNINA9910743257703321"]
[null,null,"Autore",null,"Taraate Vaibbhav"]
[null,null,"Titolo",null,"Digital design techniques and exercises : a practice book for digital logic design / / Vaibbhav Taraate"]
[null,null,"Pubbl/distr/stampa",null,"Gateway East, Singapore : , : Springer, , [2022]"]
[{"$nulls":4},"©2022"]
[null,null,"ISBN",null,"981-16-5955-9"]
[{"$nulls":4},"981-16-5954-0"]
[null,null,"Descrizione fisica",null,"1 online resource (204 pages)"]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Logic design - Data processing"]
[{"$nulls":4},"Logic design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Intro -- Preface -- Acknowledgements -- Contents -- About the Author -- 1 Basics of Digital Design -- 1.1 Digital Logic and the Evolution -- 1.2 The Important Considerations -- 1.2.1 Area of the Design -- 1.2.2 Speed of the Design -- 1.2.3 Power -- 1.3 Logic Gates -- 1.4 De Morgan's Theorems -- 1.4.1 NAND is Equal to Bubbled OR -- 1.4.2 NOR is Equal to Bubbled AND -- 1.5 Multiplexer as Universal Logic -- 1.6 Optimization Goals and Applications in VLSI Context -- 1.7 Exercises -- 1.7.1 Exercise 1: Use of the Logical Expressions to Get the Logic Equivalent -- 1.7.2 Exercise 2: Cascade Logic and How to Get Logic Expression? -- 1.7.3 Exercise 3: Complement Logic -- 1.7.4 Exercise 4: Logic Expression for the Cascade Logic -- 1.7.5 Exercise 5: Output Expression for the Cascade Logic -- 1.7.6 Exercise 6: Propagation Delay for the Cascade Logic -- 1.7.7 Exercise 7: Logic Gate Output Expression -- 1.7.8 Exercise 8: Propagation Delay for the Cascade Logic -- 1.7.9 Exercise 9: The Equivalent Logic Expression -- 1.7.10 Exercise 10: The Equivalent Logic Gate -- 1.8 Important Takeaways -- 2 Design Using Universal Logic -- 2.1 What Is Universal Logic? -- 2.2 Universal Gates -- 2.2.1 NAND -- 2.2.2 NOR -- 2.2.3 Other Application-Specific Universal Gates -- 2.3 Multiplexers -- 2.3.1 Design Using 2:1 Mux -- 2.3.2 4:1 MUX Using 2:1 Mux -- 2.3.3 Design Using Multiplexers -- 2.4 Exercises -- 2.4.1 Exercise 1: Design Using Universal Gates -- 2.4.2 Exercise 2: Design Using the MUX -- 2.4.3 "]
[{"$nulls":4},"Exercise 3: Design Using MUX -- 2.4.4 Exercise 4: Design Using Custom Gates -- 2.4.5 Exercise 5: Optimization Exercise -- 2.4.6 Exercise 7: Design Using the MUX -- 2.4.7 Exercise 8: Design Using MUX -- 2.4.8 Exercise 9: Design Using Custom Gates -- 2.5 Applications and Use in VLSI Context -- 2.6 Important Takeaways -- 3 Combinational Design Resources -- 3.1 Code Converters."]
[{"$nulls":4},"3.1.1 Three-Bit Binary-to-Gray Code Converter -- 3.1.2 3-Bit Gray-to-Binary Code Converter -- 3.2 Arithmetic Resources -- 3.2.1 Half-Adder -- 3.2.2 Half-Subtractor -- 3.2.3 Full-Adder -- 3.3 Use of Arithmetic Resources in the Design -- 3.4 Design Using Arithmetic Resources and Control Elements -- 3.5 Optimization Goals -- 3.6 Processor Logic and Need of Arithmetic Resources -- 3.7 Exercises -- 3.7.1 Exercise 1: Cascade Versus Parallel Logic -- 3.7.2 Exercise 2: Delay of the Design -- 3.7.3 Exercise 3: Speed -- 3.7.4 Exercise 4: Design to perform the Addition and Subtraction -- 3.7.5 Exercise 4: Design with the Goal to Use Resource Sharing -- 3.8 Important Takeaways -- 4 Case Study: ALU Design -- 4.1 Design Specifications and Their Role -- 4.2 What Is ALU? -- 4.3 Arithmetic Unit Design -- 4.3.1 Resources Required -- 4.3.2 How to Start Design of ALU? -- 4.3.3 How to Design the Logic -- 4.3.4 Exercise 1: Optimization of the Arithmetic Unit -- 4.3.5 Logic Unit Design -- 4.3.6 Resources Required -- 4.3.7 How to Design the Logic Unit to have Better Area? -- 4.4 ALU Design -- 4.4.1 Resource Requirement and How to Design Efficient ALU? -- 4.4.2 ALU Design to have Better Area -- 4.4.3 Exercise 2: Optimization of ALU -- 4.5 Few Important Design Guidelines -- 4.6 Important Takeaways -- 5 Practical Scenarios and the Design Techniques -- 5.1 Parallel Logic -- 5.1.1 Decoder 2 to 4 -- 5.2 Encoder -- 5.3 Encoder with Invalid Output Detection Logic -- 5.4 Exercises -- 5.4.1 Exercise 1: Design of Decoder Having Active-Low Output -- 5.4.2 Exercise 2: Design the Function Using Decoder -- 5.4.3 Exercise 3: Design Using Decoders -- 5.4.4 Exercise 4: Design Using Decoder and NAND Gates -- 5.4.5 Exercise 5: Design Using Decoders -- 5.4.6 Exercise 6: Priority Encoder Design -- 5.5 Important Takeaways -- 6 Basics of the Sequential Design."]
[{"$nulls":4},"6.1 What Is Sequential Logic Design? -- 6.2 Sequential Design Elements -- 6.3 Level Versus Edge-Triggered Logic -- 6.4 Latches and Their Use in the Design -- 6.4.1 Positive-Level-Sensitive D Latch -- 6.4.2 Negative-Level-Sensitive D Latch -- 6.5 Edge-Sensitive Elements and Their Role -- 6.5.1 Positive Edge-Sensitive D Flip-Flop -- 6.5.2 Negative Edge-Sensitive D Flip-Flop -- 6.6 Applications -- 6.6.1 Applications of the Latches -- 6.6.2 Applications of the Flip-Flop -- 6.7 Exercises -- 6.7.1 Exercise 1: Design Positive-Level-Sensitive Latch Using Multiplexers -- 6.7.2 Exercise 2: Design Negative-Level-Sensitive Latch Using Multiplexers -- 6.7.3 Exercise 3: What Is the Functionality of the Following Design? -- 6.7.4 Exercise 4: Design the Positive Edge-Sensitive Flip-Flop Using Latches -- 6.7.5 Exercise 5: Design the Negative Edge-Sensitive Flip-Flop Using Latches -- 6.7.6 Exercise 6: What Is the Operating Frequency of the Following Circuit? -- 6.7.7 Exercise 7: The Asynchronous Clear -- 6.7.8 Exercise 8: The Synchronous Clear -- 6.8 Important Takeaways -- 7 Sequential Design Techniques -- 7.1 Synchronous Design -- 7.2 Asynchronous Design -- 7.3 Why to Use Synchronous Design? -- 7.3.1 Which Elements We Should Use During Design? -- 7.4 D Flip-Flop and Use in the Design -- 7.5 Design for the given specifications -- 7.6 Design of the Synchronous Counters -- 7.7 Exercise 1: Design of the Synchronous Down-Counters -- 7.8 Exercise 2: Design of the Synchronous Gray Counter -- 7.9 Few Important Guidelines -- 7.10 Important Takeaways -- 8 Important Design Scenarios -- 8.1 MOD-3 Counter -- 8.2 The Design of MOD-3 Counter with 50% Duty "]
[{"$nulls":4},"Cycle -- 8.3 Applications and Use of Counters -- 8.3.1 Ring Counter -- 8.3.2 Johnson Counter -- 8.4 Exercises -- 8.4.1 Exercise 1: The Counter Output -- 8.4.2 Exercise 2: Find the Output Sequence."]
[{"$nulls":4},"8.4.3 Exercise 3: Operating Frequency of Design -- 8.4.4 Exercise 4: Output on 1024th Clock Cycle -- 8.4.5 Exercise 5: Output on the 4th Clock Cycle -- 8.4.6 Exercise 6: Output at 10th Clock Pulse -- 8.4.7 Exercise 7: Design the Serial Input Serial Output Shift Register -- 8.5 Important Takeaways -- 9 FSM Design Techniques -- 9.1 What Is FSM? -- 9.1.1 Moore FSM -- 9.1.2 Mealy FSM -- 9.1.3 Moore Versus Mealy FSM -- 9.2 State Encoding Methods -- 9.3 Moore FSM Design -- 9.4 Mealy FSM Design -- 9.5 Applications and Design Strategies -- 9.6 Exercises -- 9.6.1 Exercise 1: Moore Machine State Diagram -- 9.6.2 Exercise 2: Mealy Machine -- 9.6.3 Exercise 3: One-Hot Encoding -- 9.6.4 Exercise 4: FSM Area and Power Optimization -- 9.7 Important Takeaways -- 10 Advanced Design Techniques-1 -- 10.1 Various Paths in the Design -- 10.2 Data and Control Paths -- 10.3 Mealy Sequence Detector Design -- 10.4 Data and Control Path Design Techniques -- 10.5 Flip-Flop Timing Parameters -- 10.6 Example on Performance Improvement of the Design -- 10.7 Exercises -- 10.7.1 Exercise 1: Maximum Operating Frequency -- 10.7.2 Exercise 2: Timing Paths -- 10.7.3 Exercise 3: Maximum Operating Frequency -- 10.7.4 Exercise 4: Positive Clock Skew and Maximum Operating Frequency for the Design -- 10.7.5 Exercise 5: Negative Clock Skew and Maximum Operating Frequency for the Design -- 10.8 Important Takeaways -- 11 Advanced Design Techniques-2 -- 11.1 Multiple Clock Domain Designs -- 11.2 Metastability -- 11.3 Control Path Synchronizer -- 11.4 Data Path Synchronizer -- 11.5 Multiple Power Domain Designs -- 11.6 Architecture-Level Designs -- 11.7 How We Can Improve the Design Performance -- 11.8 The Digital Systems and Design -- 11.9 Exercises -- 11.9.1 Exercise 1: FIFO Depth Calculation -- 11.9.2 Exercise 2: FIFO Depth Calculation -- 11.9.3 Exercise 3: FIFO Depth Calculation."]
[{"$nulls":4},"11.9.4 Exercise 4: FIFO Depth Calculation -- 11.9.5 Exercise 5: FIFO Depth Calculation -- 11.10 Important Takeaways -- 12 System Design and Considerations -- 12.1 System Design -- 12.2 What We Need to Think About? -- 12.3 Important Considerations -- 12.4 Let Us Understand the Microprocessor Capabilities -- 12.5 Control Signal Generation Logic -- 12.6 IO Devices and Communication with the Processor -- 12.7 Memory Devices and Communication with the Processor -- 12.8 Design Scenarios and Optimization -- 12.9 Concluding Comments -- Index."]