{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":32,"n_cols":5,"rows_kept":32,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[11,2,11,3],[11,4,11,5],[12,2,12,3],[12,4,12,5],[13,2,13,3],[13,4,13,5],[14,2,14,3],[15,2,15,3],[16,2,16,3],[17,2,17,3],[18,2,18,3],[19,2,19,3],[25,2,25,3],[26,2,26,3],[29,2,29,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNIPARTHENOPE000013454"]
[null,null,"Autore",null,"Dabin, Jean"]
[null,null,"Titolo",null,"Théorie générale du droit / Jean Dabin"]
[null,null,"Pubbl/distr/stampa",null,"Bruxelles : Bruylant, 1953"]
[null,null,"Edizione",null,"[2. éd. rev. et corrigée]"]
[null,null,"Descrizione fisica",null,"325 p. ; 25 cm"]
[null,null,"Disciplina",null,"340.11"]
[null,null,"Collocazione",null,"340.11/105"]
[null,null,"Lingua di pubblicazione",null,"Francese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,"2.","Record Nr.",null,"UNINA9910254335203321"]
[null,null,"Autore",null,"Wang Ran"]
[null,null,"Titolo",null,"Testing of Interposer-Based 2.5D Integrated Circuits / / by Ran Wang, Krishnendu Chakrabarty"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer International Publishing : , : Imprint : Springer, , 2017"]
[null,null,"ISBN",null,"3-319-54714-3"]
[null,null,"Edizione",null,"[1st ed. 2017.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XIV, 182 p. 118 illus., 102 illus. in color.)"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Logic design"]
[{"$nulls":4},"Circuits and Systems"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"Logic Design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references at the end of each chapters."]
[null,null,"Nota di contenuto",null,"Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-."]
[null,null,null,"Sommario/riassunto","This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay "]
[{"$nulls":4},"faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs."]