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[null,"1.","Record Nr.",null,"UNIPARTHENOPE000012389"]
[null,null,"Titolo",null,"Il disagio degli economisti / scritti di Robert L. Heilbroner ... et al.] ; a cura di Riccardo Fiorito"]
[null,null,"Pubbl/distr/stampa",null,"Firenze : La nuova Italia, 1976"]
[null,null,"Descrizione fisica",null,"XII, 222 p. : ill. ; 21 cm"]
[null,null,"Collana",null,"Dimensioni ; 37"]
[null,null,"Disciplina",null,"330.01"]
[{"$nulls":4},"330.1"]
[null,null,"Collocazione",null,"031/90"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Pubbl. originariamente in periodici vari"]
[{"$nulls":4},"Trad. R. Pasqualini, J. Halevi"]
[null,"2.","Record Nr.",null,"UNINA9910337645003321"]
[null,null,"Autore",null,"Lee Weng Fook"]
[null,null,"Titolo",null,"Learning from VLSI Design Experience  / / by Weng Fook Lee"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019"]
[null,null,"ISBN",null,"3-030-03238-8"]
[null,null,"Edizione",null,"[1st ed. 2019.]"]
[null,null,"Descrizione fisica",null,"1 online resource (xxix, 214 pages)"]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Electronics"]
[{"$nulls":4},"Microelectronics"]
[{"$nulls":4},"Circuits and Systems"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"Electronics and Microelectronics, Instrumentation"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. ."]
[null,null,null,"Sommario/riassunto","This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library "]
[{"$nulls":4},"influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience."]