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[null,"1.","Record Nr.",null,"UNINA9911020217903321"]
[null,null,"Autore",null,"Lee Weng Fook"]
[null,null,"Titolo",null,"Verilog Coding for Logic Synthesis"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : Wiley Interscience Imprint, 2003"]
[null,null,"ISBN",null,"9786610556526"]
[{"$nulls":4},"9781280556524"]
[{"$nulls":4},"1280556528"]
[{"$nulls":4},"9780471457558"]
[{"$nulls":4},"0471457558"]
[{"$nulls":4},"9780470356920"]
[{"$nulls":4},"0470356928"]
[{"$nulls":4},"9780471457565"]
[{"$nulls":4},"0471457566"]
[null,null,"Edizione",null,"[1st edition]"]
[null,null,"Descrizione fisica",null,"1 online resource (1 v.) : ill"]
[null,null,"Disciplina",null,"621.395"]
[null,null,"Soggetti",null,"Digital electronics"]
[{"$nulls":4},"Logic circuits - Computer-aided design"]
[{"$nulls":4},"Verilog (Computer hardware description language)"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Introduction -- Asic design flow -- Verilog coding -- Coding style : best-known method for synthesis -- Design example of programmable timer -- Design example of programmable logic block for peripheral interface."]
[null,null,null,"Sommario/riassunto","Provides a practical approach to Verilog design and problem solving. Bulk of the book deals with practical design problems that design engineers solve on a daily basis. Includes over 90 design examples. There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. Book is suitable for use as a textbook in EE departments that have VLSI courses"]