{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":29,"n_cols":5,"rows_kept":29,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[13,2,13,3],[14,2,14,3],[15,2,15,3],[16,2,16,3],[17,2,17,3],[21,2,21,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9911019209203321"]
[null,null,"Autore",null,"Ytterdal Trond"]
[null,null,"Titolo",null,"Device modeling for analog and RF CMOS circuit design / / Trond Ytterdal, Yuhua Cheng, Tor A. Fjeldly"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, NJ, : Wiley, c2003"]
[null,null,"ISBN",null,"9786610271870"]
[{"$nulls":4},"9781280271878"]
[{"$nulls":4},"1280271876"]
[{"$nulls":4},"9780470353257"]
[{"$nulls":4},"0470353252"]
[{"$nulls":4},"9780470864340"]
[{"$nulls":4},"0470864346"]
[{"$nulls":4},"9780470863800"]
[{"$nulls":4},"0470863803"]
[null,null,"Descrizione fisica",null,"1 online resource (308 p.)"]
[null,null,"Disciplina",null,"621.39/5"]
[null,null,"Soggetti",null,"Metal oxide semiconductors, Complementary - Computer-aided design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Device Modeling for Analog and RF CMOS Circuit Design; Contents; Preface; 1 MOSFET Device Physics and Operation; 1.1 Introduction; 1.2 The MOS Capacitor; 1.2.1 Interface Charge; 1.2.2 Threshold Voltage; 1.2.3 MOS Capacitance; 1.2.4 MOS Charge Control Model; 1.3 Basic MOSFET Operation; 1.4 Basic MOSFET Modeling; 1.4.1 Simple Charge Control Model; 1.4.2 The Meyer Model; 1.4.3 Velocity Saturation Model; 1.4.4 Capacitance Models; 1.4.5 Comparison of Basic MOSFET Models; 1.4.6 Basic Small-signal Model; 1.5 Advanced MOSFET Modeling; 1.5.1 Modeling Approach; 1.5.2 Nonideal Effects"]
[{"$nulls":4},"1.5.3 Unified MOSFET C-V ModelReferences; 2 MOSFET Fabrication; 2.1 Introduction; 2.2 Typical Planar Digital CMOS Process Flow; 2.3 RF CMOS Technology; References; 3 RF Modeling; 3.1 Introduction; 3.2 Equivalent Circuit Representation of MOS Transistors; 3.3 High-frequency Behavior of MOS Transistors and AC Small-signal Modeling; 3.3.1 Requirements for MOSFET Modeling for RF Applications; 3.3.2 Modeling of the Intrinsic Components; 3.3.3 HF Behavior and Modeling of the Extrinsic Components; 3.3.4 Non-quasi-static Behavior; 3.4 "]
[{"$nulls":4},"Model Parameter Extraction"]
[{"$nulls":4},"3.4.1 RF Measurement and De-embedding Techniques3.4.2 Parameter Extraction; 3.5 NQS Model for RF Applications; References; 4 Noise Modeling; 4.1 Noise Sources in a MOSFET; 4.2 Flicker Noise Modeling; 4.2.1 The Physical Mechanisms of Flicker Noise; 4.2.2 Flicker Noise Models; 4.2.3 Future Work in Flicker Noise Modeling; 4.3 Thermal Noise Modeling; 4.3.1 Existing Thermal Noise Models; 4.3.2 HF Noise Parameters; 4.3.3 Analytical Calculation of the Noise Parameters; 4.3.4 Simulation and Discussions; 4.3.5 Induced Gate Noise Issue; References; 5 Proper Modeling for Accurate Distortion Analysis"]
[{"$nulls":4},"5.1 Introduction5.2 Basic Terminology; 5.3 Nonlinearities in CMOS Devices and Their Modeling; 5.4 Calculation of Distortion in Analog CMOS Circuits; References; 6 The BSIM4 MOSFET Model; 6.1 An Introduction to BSIM4; 6.2 Gate Dielectric Model; 6.3 Enhanced Models for Effective DC and AC Channel Length and Width; 6.4 Threshold Voltage Model; 6.4.1 Enhanced Model for Nonuniform Lateral Doping due to Pocket (Halo) Implant; 6.4.2 Improved Models for Short-channel Effects; 6.4.3 Model for Narrow Width Effects; 6.4.4 Complete Threshold Voltage Model in BSIM4; 6.5 Channel Charge Model"]
[{"$nulls":4},"6.6 Mobility Model6.7 Source/Drain Resistance Model; 6.8 I-V Model; 6.8.1 I-V Model When rdsMod = 0 (R(DS)(V) 0); 6.8.2 I-V Model When rdsMod = 1 (R(DS)(V) = 0); 6.9 Gate Tunneling Current Model; 6.9.1 Gate-to-substrate Tunneling Current I(GB); 6.9.2 Gate-to-channel and Gate-to-S/D Currents; 6.10 Substrate Current Models; 6.10.1 Model for Substrate Current due to Impact Ionization of Channel Current; 6.10.2 Models for Gate-induced Drain Leakage (GIDL) and Gate-induced Source Leakage (GISL) Currents; 6.11 Capacitance Models; 6.11.1 Intrinsic Capacitance Models"]
[{"$nulls":4},"6.11.2 Fringing/Overlap Capacitance Models"]
[null,null,null,"Sommario/riassunto","Bridges the gap between device modelling and analog circuit design.Includes dedicated software enabling actual circuit design.Covers the three significant models: BSIM3, Model 9 &, and EKV.Presents practical guidance on device development and circuit implementation.The authors offer a combination of extensive academic and industrial experience."]