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[null,"1.","Record Nr.",null,"UNINA9911007371003321"]
[null,null,"Titolo",null,"System-on-chip : next generation electronics / / edited by Bashir M. Al-Hashimi"]
[null,null,"Pubbl/distr/stampa",null,"London, : Institution of Electrical Engineers, c2006"]
[null,null,"ISBN",null,"1-282-15174-6"]
[{"$nulls":4},"9786612151743"]
[{"$nulls":4},"1-61583-318-8"]
[{"$nulls":4},"1-84919-020-8"]
[null,null,"Descrizione fisica",null,"1 online resource (940 p.)"]
[null,null,"Collana",null,"IEE circuits, devices and systems series ; ; 18"]
[null,null,"Disciplina",null,"621.381"]
[{"$nulls":4},"621.395"]
[null,null,"Soggetti",null,"Systems on a chip"]
[{"$nulls":4},"Embedded computer systems"]
[{"$nulls":4},"Microelectronics"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Contents; PART I - System-level design; 1 Multi-criteria decision making in embedded system design; 2 System-level performance analysis - the SymTA/S approach; 3 Analysis and optimisation of heterogeneous real-time embedded systems; 4 Hardware/software partitioning of operating systems: focus on deadlock avoidance; Models of computation in the design process; 6 Architecture description languages for programmable embedded systems; PART II -Embedded software; 7 Concurrent models of computation for embedded software; 8 Retargetable compilers and architecture exploration for embedded processors"]
[{"$nulls":4},"9 Software power optimisationPART III -Power reduction and management; 10 Power-efficient data management for dynamic applications; 11 Low power system scheduling, synthesis and displays; 12 Power minimisation techniques at the RT-level and below; 13 Leakage power analysis and reduction for nano-scale circuits; PART IV - Reconfigurable computing; 14 Reconfigurable computing: architectures and design methods; PART V-Architectural synthesis; 15 CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip; 16 Clock-less circuits and system synthesis"]
[{"$nulls":4},"PART VI - Network-on-chip17 Network-on-chip architectures and "]
[{"$nulls":4},"design methods; 18 Asynchronous on-chip networks; PART VII -Simulation and verification; 19 Covalidation of complex hardware/software systems; 20 Hardware/software cosimulation from interface perspective; 21 System-level validation using formal techniques; PART VIII - Manufacturing test; 22 Efficient modular testing and test resource partitioning for core-based SoCs; 23 On-chip test infrastructure design for optimal multi-site testing; 24 High-resolution flash time-to-digital conversion and calibration for system-on-chip testing"]
[{"$nulls":4},"25 Yield and reliability prediction forDSM circuits"]
[null,null,null,"Sommario/riassunto","System-on-Chip (SoC) represents the next major market for microelectronics, and there is considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. SoC is an expanding field, at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum which includes books, journals, and conference proceedings.The book provides a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas, provided by leading experts in th"]