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[null,"1.","Record Nr.",null,"UNINA9911006647203321"]
[null,null,"Autore",null,"Lilja David J"]
[null,null,"Titolo",null,"Designing digital computing systems with Verilog / / David J. Lilja and Sachin S. Sapatnekar"]
[null,null,"Pubbl/distr/stampa",null,"Cambridge ; ; New York, : Cambridge University Press, 2005"]
[null,null,"ISBN",null,"1-107-16031-6"]
[{"$nulls":4},"1-280-74962-8"]
[{"$nulls":4},"9786610749621"]
[{"$nulls":4},"0-511-26247-7"]
[{"$nulls":4},"0-511-26486-0"]
[{"$nulls":4},"0-511-26558-1"]
[{"$nulls":4},"0-511-26328-7"]
[{"$nulls":4},"0-511-33160-6"]
[{"$nulls":4},"0-511-60705-9"]
[{"$nulls":4},"0-511-26409-7"]
[null,null,"Descrizione fisica",null,"1 online resource (ix, 160 pages) : digital, PDF file(s)"]
[null,null,"Disciplina",null,"621.39/2"]
[null,null,"Soggetti",null,"Verilog (Computer hardware description language)"]
[{"$nulls":4},"Electronic digital computers - Design and construction"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Title from publisher's bibliographic system (viewed on 05 Oct 2015)."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Cover; Half-title; Title; Copyright; Contents; Preface; 1 Controlling complexity; 2 A Verilogical place to start; 3 Defining the instruction set architecture; 4 Algorithmic behavioral modeling; 5 Building an assembler for VeSPA; 6 Pipelining; 7 Implementation of the pipelined processor; 8 Verification; APPENDIX A The VeSPA instruction set architecture (ISA); APPENDIX B The VASM assembler; Index"]
[null,null,null,"Sommario/riassunto","This book serves both as an introduction to computer architecture and as a guide to using a hardware description language (HDL) to design, model and simulate real digital systems. The book starts with an introduction to Verilog - the HDL chosen for the book since it is widely used in industry and straightforward to learn. Next, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined - this is a real working device that has been built and tested at the University of Minnesota by the authors. The VeSPA ISA is used throughout the remainder of the book to "]
[{"$nulls":4},"demonstrate how behavioural and structural models can be developed and intermingled in Verilog. Although Verilog is used throughout, the lessons learned will be equally applicable to other HDLs. Written for senior and graduate students, this book is also an ideal introduction to Verilog for practising engineers."]