{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":3,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":78,"n_cols":5,"rows_kept":78,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[12,2,12,3],[13,2,13,3],[17,2,17,3],[20,2,20,3],[20,4,20,5],[21,2,21,3],[21,4,21,5],[22,2,22,3],[22,4,22,5],[23,2,23,3],[24,2,24,3],[31,2,31,3],[32,2,32,3],[33,2,33,3],[35,2,35,3],[37,2,37,3],[38,2,38,3],[42,2,42,3],[44,2,44,3],[44,4,44,5],[45,2,45,3],[45,4,45,5],[46,2,46,3],[47,2,47,3],[48,2,48,3],[49,2,49,3],[50,2,50,3],[51,2,51,3],[54,2,54,3],[55,2,55,3],[69,2,69,3],[70,2,70,3],[74,2,74,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910458692303321"]
[null,null,"Titolo",null,"What can we learn from nutrition impact evaluations? [[electronic resource] ] : lessons from a review of interventions to reduce child malnutrition in developing countries"]
[null,null,"Pubbl/distr/stampa",null,"Washington D.C., : World Bank, 2010"]
[null,null,"ISBN",null,"1-282-90620-8"]
[{"$nulls":4},"9786612906206"]
[{"$nulls":4},"0-8213-8407-4"]
[null,null,"Descrizione fisica",null,"1 online resource (294 p.)"]
[null,null,"Collana",null,"Independent Evaluation Group Studies"]
[null,null,"Disciplina",null,"362.19639"]
[null,null,"Soggetti",null,"Nutrition - Developing countries"]
[{"$nulls":4},"Malnutrition in children"]
[{"$nulls":4},"Electronic books."]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references (p. 84-88)."]
[null,null,"Nota di contenuto",null,"Cover; Title Page; Copyright; Table of Contents; Abbreviations; Acknowledgments; Executive Summary; Chapter 1: Introduction; Chapter 2: Findings from Recent Nutrition Impact Evaluations; Chapter 3: Evaluations of World Bank Nutrition Support; Chapter 4: Conclusions; Appendix A: The Impact Evaluations Reviewed; Appendix B: Impact Evaluations of Height, Height for Age, and Stunting; Appendix C: Impact Evaluations of Weight, Weight for Age, and Underweight; Appendix D: Impact Evaluations of Weight for Height and Wasting; Appendix E: Impact Evaluations of Birthweight and Low Birthweight"]
[{"$nulls":4},"Appendix F: Impact Evaluation BasicsEndnotes; Bibliography; Back cover"]
[null,null,null,"Sommario/riassunto","High levels of child malnutrition in developing countries contribute to mortality and have long-term consequences for children's cognitive development and earnings as adults. Recent impact evaluations show that many different interventions have had an impact on children's anthropometric outcomes (height, weight, and birth weight), but there is no simple answer to the question \"What works?\" to address the problem. Similar interventions have widely different results in different settings, owing to differences in local context, the causes and severity of malnutrition, and the capacity for program"]
[null,"2.","Record Nr.",null,"UNINA9911004891303321"]
[null,null,"Autore",null,"Hasnas John"]
[null,null,"Titolo",null,"Trapped : when acting ethically is against the law  / / John Hasnas"]
[null,null,"Pubbl/distr/stampa",null,"Washington, D.C., : Cato Institute, 2006"]
[null,null,"ISBN",null,"9786611905675"]
[{"$nulls":4},"9781933995403"]
[{"$nulls":4},"1933995408"]
[{"$nulls":4},"9781281905673"]
[{"$nulls":4},"1281905674"]
[{"$nulls":4},"9781598759136"]
[{"$nulls":4},"1598759132"]
[null,null,"Edizione",null,"[1st ed.]"]
[null,null,"Descrizione fisica",null,"1 online resource (135 p.)"]
[null,null,"Disciplina",null,"346.7306648"]
[{"$nulls":4},"364.16/80973"]
[null,null,"Soggetti",null,"White collar crimes - United States"]
[{"$nulls":4},"Crime - United States"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references."]
[null,null,"Nota di contenuto",null,"Dedications; Table of Contents; 1. Introduction; Part I: The Evolution of White-Collar Crime; 2. The Nature of White-Collar Crime; 3. Problems of Enforcement; 4. The Solutions - Corporate Criminal Responsibility; 5. The Solutions - New Offenses; 6. The Solutions - The Organizational Sentencing Guidelines; Part II: The Effect of the Federal Campaign; 7. Five Ethical Dilemmas; 8. Organizational Justice; 9. Privacy; 10. Confidentiality; 11. Trust; 12. Ethical Self-Assessment; 13. Conclusion; Notes; Index; About the Author; Cato Institute"]
[null,null,null,"Sommario/riassunto","Since Enron's collapse in 2002, the federal government has stepped up its campaign against white-collar crime. This book reveals how the government's effort to enforce legal rules has created a Catch-22 legal environment in which businesspeople must either act unethically or illegally."]
[null,"3.","Record Nr.",null,"UNINA9910485025903321"]
[null,null,"Titolo",null,"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers / / edited by Lars Svensson, José Monteiro"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009"]
[null,null,"ISBN",null,"3-540-95948-3"]
[null,null,"Edizione",null,"[1st ed. 2009.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XIII, 462 p.)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 5349"]
[null,null,"Classificazione",null,"DAT 190f"]
[{"$nulls":4},"ELT 272f"]
[{"$nulls":4},"SS 4800"]
[null,null,"Disciplina",null,"620/.004202825536"]
[null,null,"Soggetti",null,"Logic design"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Electronic digital computers - Evaluation"]
[{"$nulls":4},"Computer arithmetic and logic units"]
[{"$nulls":4},"Computer storage devices"]
[{"$nulls":4},"Memory management (Computer science)"]
[{"$nulls":4},"Electronic circuits"]
[{"$nulls":4},"Logic Design"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"System Performance and Evaluation"]
[{"$nulls":4},"Arithmetic and Logic Structures"]
[{"$nulls":4},"Computer Memory Structure"]
[{"$nulls":4},"Electronic Circuits and Systems"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Session 1: Low-Leakage and Subthreshold Circuits -- Subthreshold FIR Filter Architecture for Ultra Low Power Applications -- Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs -- Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits -- Design and Evaluation of Mixed 3T-4T FinFET "]
[{"$nulls":4},"Stacks for Leakage Reduction -- Session 2: Low-Power Methods and Models -- Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating -- Intelligate: Scalable Dynamic Invariant Learning for Power Reduction -- Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption -- Power-Aware Design via Micro-architectural Link to Implementation -- Untraditional Approach to Computer Energy Reduction -- Session 3: Arithmetic and Memories -- Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication -- Power Optimization of Parallel Multipliers in Systems with Variable Word-Length -- A Design Space Comparison of 6T and 8T SRAM Core-Cells -- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization -- Session 4: Variability and Statistical Timing -- Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic -- A Study on CMOS Time Uncertainty with Technology Scaling -- Static Timing Model Extraction for Combinational Circuits -- A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA -- Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power -- Session 5: Synchronization and Interconnect -- Logic Synthesis of Handshake Components Using Structural Clustering Techniques -- Fast Universal Synchronizers -- A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router -- PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels -- Session 6: Power Supplies and Switching Noise -- Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits -- A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint -- Generating Worst-Case Stimuli for Accurate Power Grid Analysis -- Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization -- Session 7: Low-Power Circuits; Reconfigurable Architectures -- Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements -- A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation -- Energy Efficient Elliptic Curve Processor -- Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing -- Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures -- Poster Session 1: Circuits and Methods -- Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers -- Ultra Low Voltage High Speed Differential CMOS Inverter -- Differential Capacitance Analysis -- Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey -- Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses -- Poster Session 2: Power and Delay Modeling -- Analytical High-Level Power Model for LUT-Based Components -- A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption -- Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates -- Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level -- Data Dependence of Delay Distribution for a Planar Bus -- Special Session: Power Optimizations Addressing Reconfigurable Architectures -- Towards Novel Approaches in Design Automation for FPGA Power Optimization -- Smart Enumeration: A Systematic Approach to Exhaustive Search -- An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs -- Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor -- Keynotes (Abstracts) -- Integration of Power Management Units onto the SoC -- Model to Hardware Matching for nm Scale Technologies -- Power and Profit: "]
[{"$nulls":4},"Engineering in the Envelope."]
[null,null,null,"Sommario/riassunto","This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008. The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures."]