{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":3,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":69,"n_cols":5,"rows_kept":69,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[10,2,10,3],[11,2,11,3],[15,2,15,3],[15,4,15,5],[16,2,16,3],[16,4,16,5],[17,2,17,3],[17,4,17,5],[18,2,18,3],[19,2,19,3],[24,2,24,3],[25,2,25,3],[26,2,26,3],[28,2,28,3],[30,2,30,3],[31,2,31,3],[35,2,35,3],[43,2,43,3],[43,4,43,5],[44,2,44,3],[44,4,44,5],[45,2,45,3],[46,2,46,3],[47,2,47,3],[48,2,48,3],[49,2,49,3],[50,2,50,3],[51,2,51,3],[61,2,61,3],[62,2,62,3],[66,2,66,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910503709603321"]
[null,null,"Autore",null,"Ventrella Mancini, Carmela"]
[null,null,"Titolo",null,"La Corte d'appello dello Stato della Città del Vaticano : pluralità di funzioni e vocazione interordinamentale / Carmela Ventrella Mancini"]
[null,null,"Pubbl/distr/stampa",null,"Bari, : Cacucci, 2020"]
[null,null,"ISBN",null,"978-88-6611-944-9"]
[null,null,"Descrizione fisica",null,"XI, 646 p. ; 24 cm"]
[null,null,"Collana",null,"Quaderni di Giornate canonistiche baresi. Nuova serie ; 7"]
[null,null,"Disciplina",null,"345.45077"]
[null,null,"Locazione",null,"FSPBC"]
[null,null,"Collocazione",null,"COLLEZ. 3011 (7)"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Segue: Sentenze e ordinanze della Corte d'appello SCV (1948-2019)"]
[{"$nulls":4},"In cop.: Università degli studi di Bari Aldo Moro"]
[null,"2.","Record Nr.",null,"UNINA9910830410003321"]
[null,null,"Autore",null,"Laplante Phillip A"]
[null,null,"Titolo",null,"Real-time systems design and analysis [[electronic resource] /] / Phillip A. Laplante"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, N.J., : Wiley, 2004"]
[null,null,"ISBN",null,"1-280-36809-8"]
[{"$nulls":4},"9786610368099"]
[{"$nulls":4},"0-470-34265-X"]
[{"$nulls":4},"0-471-64828-0"]
[{"$nulls":4},"0-471-64829-9"]
[null,null,"Edizione",null,"[3rd ed.]"]
[null,null,"Descrizione fisica",null,"1 online resource (529 p.)"]
[null,null,"Disciplina",null,"001.6"]
[{"$nulls":4},"004.33"]
[null,null,"Soggetti",null,"Real-time data processing"]
[{"$nulls":4},"System design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references (p. 475-485) and index."]
[null,null,"Nota di contenuto",null,"REAL-TIME SYSTEMS DESIGN AND ANALYSIS; CONTENTS; Preface to the Third Edition; 1 Basic Real-Time Concepts; 1.1 Terminology; 1.1.1 Systems Concepts; 1.1.2 Real-Time Definitions; 1.1.3 Events and Determinism; 1.1.4 CPU Utilization; 1.2 Real-Time System Design Issues; 1.3 Example Real-Time Systems; 1.4 Common Misconceptions; 1.5 Brief History; 1.5.1 Theoretical Advances; 1.5.2 Early Systems; 1.5.3 Hardware Developments; 1.5.4 Early Software; 1.5.5 Commercial Operating System Support; 1.6 Exercises; 2 Hardware Considerations; 2.1 Basic Architecture; 2.2 Hardware Interfacing; 2.2.1 Latching"]
[{"$nulls":4},"2.2.2 Edge versus Level Triggered2.2.3 Tristate Logic; 2.2.4 Wait States; 2.2.5 Systems Interfaces and Buses; 2.3 Central Processing Unit; 2.3.1 Fetch and Execute Cycle; 2.3.2 Microcontrollers; 2.3.3 Instruction Forms; 2.3.4 Core Instructions; 2.3.5 Addressing Modes; 2.3.6 RISC versus CISC; 2.4 Memory; 2.4.1 Memory Access; 2.4.2 Memory Technologies; 2.4.3 Memory Hierarchy; 2.4.4 Memory Organization; 2.5 Input/Output; 2.5.1 Programmed Input/Output; 2.5.2 Direct Memory Access; 2.5.3 Memory-Mapped Input/Output; 2.5.4 Interrupts; 2.6 Enhancing Performance; 2.6.1 Locality of Reference; 2.6.2 Cache"]
[{"$nulls":4},"2.6.3 Pipelining2.6.4 Coprocessors; 2.7 Other Special Devices; 2.7.1 Applications-Specific Integrated Circuits; 2.7.2 Programmable Array "]
[{"$nulls":4},"Logic/Programmable Logic Array; 2.7.3 Field-Programmable Gate Arrays; 2.7.4 Transducers; 2.7.5 Analog/Digital Converters; 2.7.6 Digital/Analog Converters; 2.8 Non-von-Neumann Architectures; 2.8.1 Parallel Systems; 2.8.2 Flynn's Taxonomy for Parallelism; 2.9 Exercises; 3 Real-Time Operating Systems; 3.1 Real-Time Kernels; 3.1.1 Pseudokernels; 3.1.2 Interrupt-Driven Systems; 3.1.3 Preemptive-Priority Systems; 3.1.4 Hybrid Systems"]
[{"$nulls":4},"3.1.5 The Task-Control Block Model3.2 Theoretical Foundations of Real-Time Operating Systems; 3.2.1 Process Scheduling; 3.2.2 Round-Robin Scheduling; 3.2.3 Cyclic Executives; 3.2.4 Fixed-Priority Scheduling-Rate-Monotonic Approach; 3.2.5 Dynamic-Priority Scheduling: Earliest-Deadline-First Approach; 3.3 Intertask Communication and Synchronization; 3.3.1 Buffering Data; 3.3.2 Time-Relative Buffering; 3.3.3 Ring Buffers; 3.3.4 Mailboxes; 3.3.5 Queues; 3.3.6 Critical Regions; 3.3.7 Semaphores; 3.3.8 Other Synchronization Mechanisms; 3.3.9 Deadlock; 3.3.10 Priority Inversion"]
[{"$nulls":4},"3.4 Memory Management3.4.1 Process Stack Management; 3.4.2 Run-Time Ring Buffer; 3.4.3 Maximum Stack Size; 3.4.4 Multiple-Stack Arrangements; 3.4.5 Memory Management in the Task-Control-Block Model; 3.4.6 Swapping; 3.4.7 Overlays; 3.4.8 Block or Page Management; 3.4.9 Replacement Algorithms; 3.4.10 Memory Locking; 3.4.11 Working Sets; 3.4.12 Real-Time Garbage Collection; 3.4.13 Contiguous File Systems; 3.4.14 Building versus Buying Real-Time Operating Systems; 3.4.15 Selecting Real-Time Kernels; 3.5 Case Study: POSIX; 3.5.1 Threads; 3.5.2 POSIX Mutexes and Condition Variables"]
[{"$nulls":4},"3.5.3 POSIX Semaphores"]
[null,null,null,"Sommario/riassunto","The leading guide to real-time systems design-revised and updatedThis third edition of Phillip Laplante's bestselling, practical guide to building real-time systems maintains its predecessors' unique holistic, systems-based approach devised to help engineers write problem-solving software. Dr. Laplante incorporates a survey of related technologies and their histories, complete with time-saving practical tips, hands-on instructions, C code, and insights into decreasing ramp-up times.Real-Time Systems Design and Analysis, Third Edition is essential for students and practicing sof"]
[null,"3.","Record Nr.",null,"UNINA9910483189703321"]
[null,null,"Titolo",null,"FSTTCS 2006: Foundations of Software Technology and Theoretical Computer Science : 26th International Conference, Kolkata, India, December 13-15, 2006, Proceedings / / edited by S. Arun-Kumar, Naveen Garg"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2006"]
[null,null,"ISBN",null,"3-540-49995-4"]
[null,null,"Edizione",null,"[1st ed. 2006.]"]
[null,null,"Descrizione fisica",null,"1 online resource (XIII, 434 p.)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 4337"]
[null,null,"Disciplina",null,"005.1"]
[null,null,"Soggetti",null,"Application software"]
[{"$nulls":4},"Computer science"]
[{"$nulls":4},"Compilers (Computer programs)"]
[{"$nulls":4},"Machine theory"]
[{"$nulls":4},"Algorithms"]
[{"$nulls":4},"Computer and Information Systems Applications"]
[{"$nulls":4},"Computer Science Logic and Foundations of Programming"]
[{"$nulls":4},"Compilers and Interpreters"]
[{"$nulls":4},"Formal Languages and Automata Theory"]
[{"$nulls":4},"Theory of Computation"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Invited Papers -- Shared-Variable Concurrency: A Proposal -- Hennessy-Plotkin-Brookes Revisited -- Approximation Algorithms for 2-Stage Stochastic Optimization Problems -- The Number of Crossing Free Configurations on Finite Point Sets in the Plane -- Contributed Papers – Track A -- Normal and Feature Approximations from Noisy Point Clouds -- Coresets for Discrete Integration and Clustering -- Self-assemblying Classes of Shapes with a Minimum Number of Tiles, and in Optimal Time -- One-Input-Face MPCVP Is Hard for L, But in LogDCFL -- Hardness of Approximation Results for the Problem of Finding the Stopping Distance in Tanner Graphs -- Multi-stack Boundary Labeling Problems -- Computing a Center-Transversal Line -- On Obtaining Pseudorandomness from Error-Correcting Codes -- Fast Edge Colorings with Fixed Number of Colors to Minimize "]
[{"$nulls":4},"Imbalance -- Zero Error List-Decoding Capacity of the q/(q–1) Channel -- Fast Exponential Algorithms for Maximum r-Regular Induced Subgraph Problems -- Solving Connected Dominating Set Faster Than 2 n  -- Linear-Time Algorithms for Two Subtree-Comparison Problems on Phylogenetic Trees with Different Species -- Computationally Sound Symbolic Secrecy in the Presence of Hash Functions -- Some Results on Average-Case Hardness Within the Polynomial Hierarchy -- Unbiased Rounding of Rational Matrices -- Contributed Papers – Track B -- Rational Behaviour and Strategy Construction in Infinite Multiplayer Games -- The Anatomy of Innocence Revisited -- Testing Probabilistic Equivalence Through Reinforcement Learning -- On Decidability of LTL Model Checking for Process Rewrite Systems -- Monitoring of Real-Time Properties -- A Proof System for the Linear Time ?-Calculus -- Tree Automata Make Ordinal Theory Easy -- Context-Sensitive Dependency Pairs -- On Reduction Criteriafor Probabilistic Reward Models -- Distributed Synthesis for Well-Connected Architectures -- The Meaning of Ordered SOS -- Almost Optimal Strategies in One Clock Priced Timed Games -- Expressivity Properties of Boolean BI Through Relational Models -- On Continuous Timed Automata with Input-Determined Guards -- Safely Freezing LTL -- Branching Pushdown Tree Automata -- Validity Checking for Finite Automata over Linear Arithmetic Constraints -- Game Semantics for Higher-Order Concurrency."]
[null,null,null,"Sommario/riassunto","This book constitutes the refereed proceedings of the 26th International Conference on the Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2006, held in Kolkata, India, in December 2006. It contains 38 papers that cover a broad variety of current topics from the theory of computing, ranging from formal methods, discrete mathematics, complexity theory, and automata theory to theoretical computer science in general."]