{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":33,"n_cols":5,"rows_kept":33,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[10,2,10,3],[11,2,11,3],[12,2,12,3],[13,2,13,3],[14,2,14,3],[15,2,15,3],[19,2,19,3],[20,2,20,3],[24,2,24,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910810547003321"]
[null,null,"Autore",null,"Voldman Steven H"]
[null,null,"Titolo",null,"Electrical overstress (EOS) : devices, circuits and systems / / Steven H. Voldman"]
[null,null,"Pubbl/distr/stampa",null,"Chichester, West Sussex, U.K., : John Wiley & Sons Inc., 2014"]
[null,null,"ISBN",null,"9781118703335"]
[{"$nulls":4},"1118703332"]
[{"$nulls":4},"9781118703328"]
[{"$nulls":4},"1118703324"]
[{"$nulls":4},"9781118703342"]
[{"$nulls":4},"1118703340"]
[null,null,"Edizione",null,"[1st ed.]"]
[null,null,"Descrizione fisica",null,"1 online resource (370 p.)"]
[null,null,"Collana",null,"ESD series"]
[null,null,"Classificazione",null,"TEC008010"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Semiconductors - Failures"]
[{"$nulls":4},"Semiconductors - Protection"]
[{"$nulls":4},"Transients (Electricity)"]
[{"$nulls":4},"Overvoltage"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Electrical Overstress (EOS): Devices, Circuits and Systems; Contents; About the Author; Preface; Acknowledgements; 1 Fundamentals of Electrical Overstress; 1.1 Electrical Overstress; 1.1.1 The Cost of Electrical Overstress; 1.1.2 Product Field Returns - The Percentage that is Electrical Overstress; 1.1.3 Product Field Returns - No Defect Found versus Electrical Overstress; 1.1.4 Product Failures - Failures in Integrated Circuits; 1.1.5 Classification of Electrical Overstress Events; 1.1.6 Electrical Over-Current; 1.1.7 Electrical Over-Voltage; 1.1.8 Electrical Over-Power"]
[{"$nulls":4},"1.2 De-Mystifying Electrical Overstress1.2.1 Electrical Overstress Events; 1.3 Sources of Electrical Overstress; 1.3.1 Sources of Electrical Overstress in Manufacturing Environment; 1.3.2 Sources of Electrical Overstress in Production Environments; 1.4 Misconceptions of Electrical Overstress; 1.5 Minimization of Electrical Overstress Sources; 1.6 Mitigation of Electrical Overstress; 1.7 Signs of Electrical Overstress Damage; 1.7.1 Signs of Electrical Overstress Damage - The Electrical Signature; 1.7.2 Signs of Electrical Overstress Damage - The Visual "]
[{"$nulls":4},"Signature"]
[{"$nulls":4},"1.8 Electrical Overstress and Electrostatic Discharge1.8.1 Comparison of High and Low Current EOS versus ESD Events; 1.8.2 Electrical Overstress and Electrostatic Discharge Differences; 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities; 1.8.4 Comparison of EOS versus ESDWaveforms; 1.8.5 Comparison of EOS versus ESD Event Failure Damage; 1.9 Electromagnetic Interference; 1.9.1 Electrical Overstress Induced Electromagnetic Interference; 1.10 Electromagnetic Compatibility; 1.11 Thermal Over-Stress; 1.11.1 Electrical Overstress and Thermal Overstress"]
[{"$nulls":4},"1.11.2 Temperature Dependent Electrical Overstress1.11.3 Electrical Overstress and Melting Temperature; 1.12 Reliability Technology Scaling; 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve; 1.12.2 The Shrinking Reliability Design Box; 1.12.3 The Shrinking Electrostatic Discharge Design Box; 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage; 1.13 Safe Operating Area; 1.13.1 Electrical Safe Operating Area; 1.13.2 Thermal Safe Operating Area; 1.13.3 Transient Safe Operating Area; 1.14 Summary and Closing Comments; References"]
[{"$nulls":4},"2 Fundamentals of EOS Models2.1 Thermal Time Constants; 2.1.1 The Thermal Diffusion Time; 2.1.2 The Adiabatic Regime Time Constant; 2.1.3 The Thermal Diffusion Regime Time Constant; 2.1.4 The Steady State Regime Time Constant; 2.2 Pulse Event Time Constants; 2.2.1 The ESD HBM Pulse Time Constant; 2.2.2 The ESD MM Pulse Time Constant; 2.2.3 The ESD Charged Device Model Pulse Time Constant; 2.2.4 The ESD Pulse Time Constant - Transmission Line Pulse; 2.2.5 The ESD Pulse Time Constant - Very Fast Transmission Line Pulse; 2.2.6 The IEC 61000-4-2 Pulse Time Constant"]
[{"$nulls":4},"2.2.7 The Cable Discharge Event Pulse Time Constant"]
[null,null,null,"Sommario/riassunto","\"Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today's modern world.Look inside for extensive coverage on: Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena EOS sources in today's semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures EOS failures in both semiconductor devices, circuits and system Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events) EOS protection on-chip design practices and how they differ from ESD protection networks and solutions Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA "]
[{"$nulls":4},"systems EOS testing and qualification techniques, and Practical off-chip ESD protection and system level solutions to provide more robust systems Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author's series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era\"--"]