{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":32,"n_cols":5,"rows_kept":32,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[13,2,13,3],[14,2,14,3],[15,2,15,3],[16,2,16,3],[17,2,17,3],[20,2,20,3],[21,2,21,3],[24,2,24,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910808850803321"]
[null,null,"Autore",null,"Doman David"]
[null,null,"Titolo",null,"Engineering the CMOS library : enhancing digital design kits for competitive silicon / / David Doman"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, N.J., : John Wiley & Sons, c2012"]
[null,null,"ISBN",null,"9786613621894"]
[{"$nulls":4},"9781280592065"]
[{"$nulls":4},"1280592060"]
[{"$nulls":4},"9781118273135"]
[{"$nulls":4},"1118273133"]
[{"$nulls":4},"9781118273142"]
[{"$nulls":4},"1118273141"]
[{"$nulls":4},"9781118273111"]
[{"$nulls":4},"1118273117"]
[null,null,"Edizione",null,"[1st edition]"]
[null,null,"Descrizione fisica",null,"1 online resource (343 p.)"]
[null,null,"Classificazione",null,"TEC008050"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Digital integrated circuits - Design and construction"]
[{"$nulls":4},"Metal oxide semiconductors, Complementary"]
[{"$nulls":4},"Industrial efficiency"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,"Nota di contenuto",null,"Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon; Contents; Preface; Acknowledgments; 1: Introduction; 1.1: Adding Project-Specific Functions, Drive Strengths, Views, and Corners; 1.2: What Is a DDK?; 2: Stdcell Libraries; 2.1: Lesson from the Real World: Manager's Perspective and Engineer's Perspective; 2.2: What Is a Stdcell?; 2.2.1: Combinational Functions; 2.2.2: Sequential Functions; 2.2.3: Clock Functions; 2.3: Extended Library Offerings; 2.3.1: Low-Power Support; 2.4: Boutique Library Offerings; 2.5: Concepts for Further Study; 3: IO Libraries"]
[{"$nulls":4},"3.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective 3.2: Extension Capable Architectures versus Function Complete Architectures; 3.3: Electrostatic Discharge Considerations; 3.3.1: Footprints; 3.3.2: Custom Design Versus Standard IO Design Comparison; 3.3.3: The Need for Maintaining Multiple IO Footprint Regions on an IC; 3.3.4: Circuit Under Pad; 3.4: "]
[{"$nulls":4},"Concepts for Further Study; 4: Memory Compilers; 4.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 4.2: Single Ports, Dual Ports, and ROM: The Compiler"]
[{"$nulls":4},"4.3: Nonvolatile Memories: The Block 4.4: Special-Purpose Memories: The Custom; 4.5: Concepts for Further Study; 5: Other Functions; 5.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 5.2: Phase-Locked Loops, Power-On Resets, and Other Small-Scale Integration Analogs; 5.3: Low-Power Support Structures; 5.4: Stitching Structures; 5.4.1: Core-Fill Cells; 5.4.2: IO-Fill Cells; 5.4.3: DECAP Cells; 5.4.4: CMP-Fill Cells; 5.4.5: Spare Logic Cells; 5.4.6: Probe-Point Cells; 5.4.7: Antenna Diodes; 5.4.8: Test-Debug Diodes; 5.4.9: Others"]
[{"$nulls":4},"5.5: Hard, Firm, and Soft Boxes 5.6: Concepts for Further Study; 6: Physical Views; 6.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 6.2: Picking an Architecture; 6.3: Measuring Density; 6.4: The Need and the Way to Work with Fabrication Houses; 6.5: Concepts for Further Study; 7: SPICE; 7.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 7.2: Why a Tool More Than 40 Years Old Is Still Useful; 7.3: Accuracy, Reality, and Why SPICE Results Must be Viewed with a Wary Eye; 7.4: Sufficient Parasitics"]
[{"$nulls":4},"7.5: Concepts for Further Study 8: Timing Views; 8.1: Lesson from the Real World: The Manager's Perspective and the Engineer's Perspective; 8.2: Performance Limits and Measurement; 8.3: Default Versus Conditional Arcs; 8.4: Break-Point Optimization; 8.5: A Word on Setup and Hold; 8.6: Failure Mechanisms and Roll-Off; 8.7: Supporting Efficient Synthesis; 8.7.1: SPICE, Monotonic Arrays, and Favorite Stdcells; 8.7.2: SPICE, Positive Arrays, and Useful Skew; 8.8: Supporting Efficient Timing Closure; 8.9: Design Corner Specific Timing Views; 8.10: Nonlinear Timing Views are so \"\"Old Hat\"\" . . ."]
[{"$nulls":4},"8.11: Concepts for Further Study"]
[null,null,null,"Sommario/riassunto","Shows readers how to gain the competitive edge in the  integrated circuit marketplace  This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition.  Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and"]