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[null,"1.","Record Nr.",null,"UNINA9910783433703321"]
[null,null,"Autore",null,"Piessens Tim"]
[null,null,"Titolo",null,"Design and Analysis of High Efficiency Line Drivers for xDSL"]
[null,null,"Pubbl/distr/stampa",null,"Dordrecht : , : Springer, , 2004"]
[{"$nulls":4},"©2004"]
[null,null,"ISBN",null,"1-4020-2518-1"]
[null,null,"Descrizione fisica",null,"1 online resource (258 pages)"]
[null,null,"Disciplina",null,"621.382/3"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Preliminaries -- Contents -- List of Figures -- List of Tables -- 1. INTRODUCTION -- 2. TRADITIONAL XDSL LINE DRIVERS -- 3. DESCRIBING FUNCTION ANALYSIS -- 4. BEHAVIOURAL MODELLING OF THE SOPA -- 5. DESIGN PLAN AND CAD-TOOLS -- 6. REALISATIONS IN MAINSTREAM CMOS -- 7. CONCLUSIONS -- Glossary -- Appendices -- References -- Index."]
[null,null,null,"Sommario/riassunto","Design and Analysis of High Efficiency Line Drivers for xDSL covers the most important building block of an xDSL (ADSL, VDSL, ) system: the line driver. Traditional Class AB line drivers consume more than 70 per cent of the total power budget of state-of-the-art ADSL modems. This book describes the main difficulties in designing line drivers for xDSL. The most important specifications are elaborated staring from the main properties of the channel and the signal properties. The traditional (class AB), state-of-the-art (class G) and future technologies (class K) are discussed. The main part of Design and Analysis of High Efficiency Line Drivers for xDSL describes the design of a novel architecture: the Self-Oscillating Power Amplifier or SOPA. This architecture uses a non-linear, asynchronous modulation scheme that enables highly efficient, highly linear transmission. The concept has been proven by two implementations in a digital CMOS technology: a G-Lite compliant line driver with 61 per cent efficiency and a full ADSL-VDSL downstream compliant power amplifier with 47 per cent power efficiency. The proposed architecture is fully analysed and complete design plans including CMOS sca."]