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[null,null,"Autore",null,"Zamiri Azar Kimia"]
[null,null,"Titolo",null,"Understanding Logic Locking / / by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer International Publishing : , : Imprint : Springer, , 2024"]
[null,null,"ISBN",null,"3-031-37989-6"]
[null,null,"Edizione",null,"[1st ed. 2024.]"]
[null,null,"Descrizione fisica",null,"1 online resource (385 pages)"]
[null,null,"Disciplina",null,"005.8"]
[null,null,"Soggetti",null,"Electronic circuit design"]
[{"$nulls":4},"Embedded computer systems"]
[{"$nulls":4},"Electronic circuits"]
[{"$nulls":4},"Electronics Design and Verification"]
[{"$nulls":4},"Embedded Systems"]
[{"$nulls":4},"Electronic Circuits and Systems"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP."]
[null,null,null,"Sommario/riassunto","This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO’s and DON’Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of "]
[{"$nulls":4},"abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers."]