{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":23,"n_cols":5,"rows_kept":23,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[10,2,10,3],[17,2,17,3],[18,2,18,3],[20,2,20,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910736029603321"]
[null,null,"Autore",null,"Han Donghyeon"]
[null,null,"Titolo",null,"On-Chip Training NPU - Algorithm, Architecture and SoC Design / / by Donghyeon Han, Hoi-Jun Yoo"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023"]
[null,null,"ISBN",null,"9783031342370"]
[{"$nulls":4},"3031342372"]
[null,null,"Edizione",null,"[1st ed. 2023.]"]
[null,null,"Descrizione fisica",null,"1 online resource (249 pages)"]
[null,null,"Collana",null,"Engineering Series"]
[null,null,"Disciplina",null,"621.3815"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Embedded computer systems"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Electronic Circuits and Systems"]
[{"$nulls":4},"Embedded Systems"]
[{"$nulls":4},"Processor Architectures"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion."]
[null,null,null,"Sommario/riassunto","Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC "]
[{"$nulls":4},"design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding."]