{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":29,"n_cols":5,"rows_kept":29,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[10,2,10,3],[11,2,11,3],[16,2,16,3],[16,4,16,5],[17,2,17,3],[17,4,17,5],[18,2,18,3],[19,2,19,3],[20,2,20,3],[21,2,21,3],[22,2,22,3],[23,2,23,3],[24,2,24,3],[27,2,27,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910707338803321"]
[null,null,"Autore",null,"Calkin David E."]
[null,null,"Titolo",null,"Assessing post-fire values-at-risk with a new calculation tool / / David E. Calkin [and five others]"]
[null,null,"Pubbl/distr/stampa",null,"Fort Collins, CO : , : United States Department of Agriculture, Forest Service, Rocky Mountain Research Station, , December 2007"]
[null,null,"Descrizione fisica",null,"1 online resource (ii, 32 pages) : color illustrations"]
[null,null,"Collana",null,"General technical report RMRS ; ; GTR-205"]
[null,null,"Soggetti",null,"Post-fire forest management"]
[{"$nulls":4},"Forest fires - Environmental aspects"]
[{"$nulls":4},"Forest fires - Economic aspects"]
[{"$nulls":4},"Fire ecology"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Title from title screen (viewed October 21, 2008)."]
[{"$nulls":4},"\"December 2007.\""]
[null,null,null,"Nota di bibliografia","Includes bibliographical references (pages 29-30)."]
[null,"2.","Record Nr.",null,"UNISA996218410303316"]
[null,null,"Titolo",null,"2005 international conference on reconfigurable computing and FPGAS"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : IEEE Computer Society, 2005"]
[null,null,"ISBN",null,"1-5090-9982-4"]
[null,null,"Descrizione fisica",null,"1 online resource (183 pages) : illustrations"]
[null,null,"Disciplina",null,"004"]
[null,null,"Soggetti",null,"Adaptive computing systems"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,"Nota di contenuto",null,"Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling, -- An image comparison circuit design,\" -- FPGA-based customizable systolic architecture for image processing applications,\" -- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method,\" -- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transform,\" -- A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays,\" -- Rapid prototyping of a self-timed ALU with FPGAs,\" -- FPGA implementation of a synchronous and self-timed neuroprocessor,\" -- On the design of two-level reconfigurable architectures,\" -- A secure self-reconfiguring architecture based on open-source hardware,\" -- Platform for intrinsic evolution of analogue neural networks,\" -- High quality uniform random number generation for massively parallel simulations in FPGA,\" -- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks,\" -- Quartz: a framework for correct and efficient reconfigurable design,\" -- Design space exploration of coarse-grain reconfigurable DSPs,\" -- Optimizing register binding in FPGAs using simulated annealing,\" -- An FPGA-based parallel sorting architecture for the Burrows Wheeler transform,\" -- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices,\" -- Applied VHDL training methodology, EDA framework and hardware implementation platform,\" -- FPGA implementation of DSVPWM modulator,\" -- A novel FPGA implementation of a welding control using a new bus architecture,\" -- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004,\" -- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3,\" "]
[{"$nulls":4},"-- VHDL core for 1024-point radix-4 FFT computation,\" -- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation,\" -- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/),\" -- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences,\" -- Hardware/software implementation of a discrete cosine transform algorithm using SystemC."]