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[null,"1.","Record Nr.",null,"UNINA9910697635503321"]
[null,null,"Titolo",null,"Buying a franchise [[electronic resource] ] : a consumer guide"]
[null,null,"Pubbl/distr/stampa",null,"[Washington, D.C.] : , : Federal Trade Commission, , [2008]"]
[null,null,"Descrizione fisica",null,"1 online resource (17 pages)"]
[null,null,"Soggetti",null,"Franchises (Retail trade) - United States"]
[{"$nulls":4},"Businesspeople - United States"]
[{"$nulls":4},"Handbooks and manuals."]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Title from title screen (viewed on Oct. 16, 2008)."]
[null,"2.","Record Nr.",null,"UNINA9910299477603321"]
[null,null,"Autore",null,"Mandal Ayan"]
[null,null,"Titolo",null,"Source-synchronous networks-on-chip : circuit and architectural interconnect modeling / / Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra"]
[null,null,"Pubbl/distr/stampa",null,"New York : , : Springer, , 2014"]
[null,null,"ISBN",null,"1-4614-9405-2"]
[null,null,"Edizione",null,"[1st ed. 2014.]"]
[null,null,"Descrizione fisica",null,"1 online resource (xiii, 143 pages) : illustrations (some color)"]
[null,null,"Collana",null,"Gale eBooks"]
[null,null,"Disciplina",null,"004.1"]
[{"$nulls":4},"620"]
[{"$nulls":4},"621.381"]
[{"$nulls":4},"621.3815"]
[null,null,"Soggetti",null,"Networks on a chip - Design"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Includes index."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work."]
[null,null,null,"Sommario/riassunto","This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art."]