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[null,"1.","Record Nr.",null,"UNINA9910546200703321"]
[null,null,"Autore",null,"Frasca, Gabriele"]
[null,null,"Titolo",null,"Dai cancelli d'acciaio : romanzo / Gabriele Frasca"]
[null,null,"Pubbl/distr/stampa",null,"[Roma], : Luca Sossella, 2011"]
[null,null,"ISBN",null,"978-88-89829-92-9"]
[null,null,"Descrizione fisica",null,"591 p. : ill. ; 24 cm"]
[null,null,"Collana",null,"Nŭmerŭs ; 52"]
[null,null,"Disciplina",null,"853.92"]
[null,null,"Locazione",null,"FLFBC"]
[null,null,"Collocazione",null,"851.91 FRA 3"]
[null,null,"Lingua di pubblicazione",null,"Italiano"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,"2.","Record Nr.",null,"UNINA9910554813203321"]
[null,null,"Autore",null,"Dinavahi Venkata"]
[null,null,"Titolo",null,"Real-time electromagnetic transient simulation of AC-DC networks / / Venkata Dinavahi, Ning Lin"]
[null,null,"Pubbl/distr/stampa",null,"Hoboken, New Jersey : , : Wiley : , : IEEE Press, , [2021]"]
[{"$nulls":4},"©2021"]
[null,null,"ISBN",null,"1-119-69547-3"]
[{"$nulls":4},"1-119-81903-2"]
[{"$nulls":4},"1-119-69549-X"]
[null,null,"Descrizione fisica",null,"1 online resource (595 pages)"]
[null,null,"Collana",null,"IEEE Press series on power and energy systems"]
[null,null,"Disciplina",null,"621.31921"]
[null,null,"Soggetti",null,"Transients (Electricity) - Simulation methods"]
[{"$nulls":4},"Electronic books."]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Cover -- Title Page -- Copyright -- Contents -- About the Authors -- Preface -- Acknowledgments -- List of Acronyms -- Chapter 1 Field Programmable Gate Arrays -- 1.1 Overview -- 1.1.1 FPGA Hardware Architecture -- 1.1.2 Configurable Logic Block -- 1.1.3 Block RAM -- 1.1.4 Digital Signal Processing Slice -- 1.2 Multiprocessing System‐on‐Chip Architecture -- 1.3 Communication -- 1.4 HIL Emulation -- 1.4.1 Vivado® High‐Level Synthesis Tool -- 1.4.2 Vivado® Top‐Level Design -- 1.4.3 Number Representation and Operations -- 1.4.4 FPGA Design Schemes -- 1.4.4.1 Pipeline Design Architecture -- 1.4.4.2 Parallel Design Architecture -- 1.4.5 FPGA Experiment -- 1.5 Summary -- Chapter 2 Hardware Emulation Building Blocks for Power System Components -- 2.1 Overview -- 2.2 Concept of HEBB -- 2.3 Numerical Integration -- 2.4 Linear Lumped Passive Elements -- 2.4.1 Model Formulation -- 2.4.1.1 Resistance R -- 2.4.1.2 Inductance L -- 2.4.1.3 Capacitance C -- 2.4.1.4 RL Branch -- 2.4.1.5 LC Branch -- 2.4.1.6 RLCG Branch -- 2.4.2 Hardware Emulation of Linear Lumped Passive Elements -- 2.5 Sources -- 2.5.1 Hardware Emulation of Sources -- 2.6 Switches -- 2.6.1 Hardware Emulation of Switches -- 2.7 Transmission Lines -- 2.7.1 Traveling Waves -- 2.7.2 Traveling Wave Model -- 2.7.2.1 Modal Transformation -- 2.7.3 Hardware Emulation of the TWM -- 2.7.3.1 Transformation Unit -- 2.7.3.2 Update Unit -- 2.7.4 Frequency Dependent Line Model -- 2.7.5 Hardware Emulation of FDLM "]
[{"$nulls":4},"-- 2.7.5.1 Convolution Unit -- 2.7.5.2 Update Unit -- 2.7.6 Universal Line Model -- 2.7.6.1 Frequency‐Domain Formulation -- 2.7.6.2 Time‐Domain Formulation -- 2.7.7 Hardware Emulation of the ULM -- 2.7.7.1 Update x Unit -- 2.7.7.2 Convolution Unit -- 2.7.7.3 Interpolation Unit -- 2.8 Network Solver -- 2.8.1 Hardware Emulation of Network Solver -- 2.8.2 Paralleled EMT Solution Algorithm."]
[{"$nulls":4},"2.8.3 MainControl Module -- 2.8.4 Real‐Time Emulation Case Study -- 2.9 Nonlinear Elements: Iterative Real‐Time EMT Solver -- 2.9.1 Compensation Method -- 2.9.2 Newton-Raphson Method -- 2.9.3 Hardware Emulation of Nonlinear Solver -- 2.9.3.1 Nonlinear Function Evaluation -- 2.9.3.2 Parallel Calculation of J and F(ikm) -- 2.9.3.3 Parallel Gauss-Jordan Elimination -- 2.9.3.4 Computing vc -- 2.9.4 Case Studies -- 2.10 Summary -- Chapter 3 Power Transformers -- 3.1 Overview -- 3.2 Nonlinear Admittance‐Based Real‐Time Transformer Model -- 3.2.1 Linear Model Formulation -- 3.2.2 Linear Module Hardware Design -- 3.2.3 Inode Unit Module -- 3.2.4 Nonlinear Model Solution -- 3.2.4.1 Preisach Hysteresis Model -- 3.2.4.2 Nonlinear Module Hardware Design -- 3.2.5 Frequency‐Dependent Eddy Current Model -- 3.2.6 Hardware Emulation of Power Transformer -- 3.2.7 Real‐Time Emulation Case Studies -- 3.2.7.1 Case I -- 3.2.7.2 Case II -- 3.3 Nonlinear Magnetic Equivalent Circuit Based Real‐time Multi‐Winding Transformer Model -- 3.3.1 Topological ST EMT Model -- 3.3.1.1 ST Operating Principle -- 3.3.1.2 Tap‐selection Algorithm -- 3.3.1.3 High‐Fidelity Nonlinear MEC‐Based ST Model -- 3.3.1.4 Iron Core Hysteresis and Eddy Currents -- 3.3.2 High‐Fidelity Nonlinear MEC‐Based ST Hardware Emulation -- 3.3.2.1 Network Transient Emulation with Embedded ST -- 3.3.3 Real‐Time Emulation Case Studies -- 3.3.3.1 Finite Element Modeling and Validation -- 3.3.3.2 Case Studies -- 3.4 Real‐Time Finite‐Element Model of Power Transformer -- 3.4.1 Magnetodynamic Problem Formulation -- 3.4.1.1 Refined TLM Solution -- 3.4.1.2 Field‐Circuit Coupling -- 3.4.2 Hardware Emulation of Finite Element Model -- 3.4.3 Case Studies -- 3.4.3.1 Results and Validation -- 3.4.3.2 Speed‐up and Scalability -- 3.5 Summary -- Chapter 4 Rotating Machines -- 4.1 Overview -- 4.2 Lumped Universal Machine (UM) Model."]
[{"$nulls":4},"4.2.1 UM Model Formulation -- 4.2.2 Interfacing UM Model with Network -- 4.2.3 UM HEBB -- 4.2.3.1 Speed &amp -- Angle Unit -- 4.2.3.2 FrmTran Unit -- 4.2.3.3 Compidq0 Unit -- 4.2.3.4 Flux &amp -- Torque Unit -- 4.2.3.5 Update &amp -- CompVc Unit -- 4.2.4 Real‐Time Emulation Case Study -- 4.2.5 Overall Power System HEBB for Real‐Time EMT Emulation -- 4.3 General Framework for State‐Space Electrical Machine Emulation -- 4.3.1 FPGA Design Approaches for Electrical Machine Emulation -- 4.3.2 State‐Space Representation of Machine Models -- 4.3.3 System Configuration on FPGA -- 4.3.3.1 Number Representation -- 4.3.3.2 Floating‐Point Implementation by VHDL -- 4.3.3.3 Fixed‐Point Implementation by Schematic -- 4.3.4 Evaluation of Designed Architectures -- 4.3.4.1 Real‐Time Emulation Accuracy Assessment -- 4.3.4.2 Off‐line Validation -- 4.3.4.3 Hardware Resource Utilization -- 4.3.5 Real‐Time Emulation Case Studies -- 4.3.5.1 Case I: Induction Motor Transients -- 4.3.5.2 Case II: Synchronous Generator Transients -- 4.3.5.3 Case III: Line Start‐Permanent Magnet Synchronous Motor Transients -- 4.3.5.4 Case IV: DC Motor Transients -- 4.4 Nonlinear Magnetic Equivalent Circuit Based Induction Machine Model -- 4.4.1 Magnetic Circuit -- 4.4.2 Interfacing of Magnetic and Electric Circuits -- 4.4.3 Electric Circuit -- 4.4.4 Nonlinear Solution of Detailed MEC -- 4.4.5 Hardware Emulation of Nonlinear MEC -- 4.4.5.1 Parallel Gauss-Jordan Elimination Unit -- 4.4.5.2 Parallel Computational Unit for Residual Vector -- 4.4.5.3 "]
[{"$nulls":4},"Nonlinear Evaluation Unit -- 4.4.6 Evaluation of Real‐Time Emulation of Induction Machine -- 4.5 Summary -- Chapter 5 Protective Relays -- 5.1 Overview -- 5.2 Hardware Emulation of Multifunction Protection System -- 5.2.1 Signal Processing HEBB -- 5.2.1.1 CORDIC HEBB -- 5.2.1.2 Symmetrical Components HEBB -- 5.2.1.3 DFT HEBB."]
[{"$nulls":4},"5.2.1.4 Zero‐Crossing Detection HEBB -- 5.2.2 Multifunction Protective System HEBB -- 5.2.2.1 Fault Detection HEBB -- 5.2.2.2 Directional Overcurrent Protection HEBB -- 5.2.2.3 Over/Under Voltage Protection HEBB -- 5.2.2.4 Distance Protection HEBB -- 5.2.2.5 Under/Over Frequency Protection HEBB -- 5.3 Test Setup and Real‐Time Results -- 5.3.1 Case I -- 5.3.2 Case II -- 5.4 Summary -- Chapter 6 Adaptive Time‐Stepping Based Real‐Time EMT Emulation -- 6.1 Overview -- 6.2 Nonlinear Solution and Adaptive Time‐Stepping Schemes -- 6.2.1 Nonlinear Element Solution Methods -- 6.2.1.1 Newton-Raphson Method -- 6.2.1.2 Piecewise Linearization (PWL) Method -- 6.2.1.3 Piecewise N‐R Method -- 6.2.2 Adaptive Time‐Stepping Schemes -- 6.2.2.1 Local Truncation Error Method -- 6.2.2.2 Iteration Count Method -- 6.2.2.3 DVDT or DIDT Method -- 6.2.3 Combinations of Adaptive Time‐Stepping Schemes -- 6.2.3.1 Measurements and Restrictions for Real‐Time Emulation -- 6.2.4 Case Studies -- 6.2.4.1 Diode Full‐Bridge Circuit -- 6.2.4.2 Power Transmission System -- 6.2.4.3 FPGA Implementation -- 6.2.4.4 Real‐Time Emulation Results -- 6.3 Adaptive Time‐Stepping Universal Line Model and Universal Machine Model for Real‐Time Hardware Emulation -- 6.3.1 Subsystem‐Based Adaptive Time‐Stepping Scheme -- 6.3.2 Adaptive Time‐Stepping ULM and UM Models -- 6.3.2.1 ULM Computation -- 6.3.2.2 Universal Machine Model Computation -- 6.3.3 Real‐Time Emulation Case Study -- 6.3.3.1 Hardware Implementation -- 6.3.3.2 Latency and Hardware Resource Utilization -- 6.3.4 Results and Validation -- 6.3.4.1 Validation of the ULM Model -- 6.3.4.2 Real‐Time Emulation Results -- 6.4 Summary -- Chapter 7 Power Electronic Switches -- 7.1 Overview -- 7.2 IGBT/Diode Nonlinear Behavioral Model -- 7.2.1 Power Diode -- 7.2.1.1 Mathematical Model -- 7.2.1.2 Hardware Module Architecture -- 7.2.2 IGBT."]
[{"$nulls":4},"7.2.2.1 Model Formulation -- 7.2.2.2 Hardware Module Architecture -- 7.2.2.3 Multiple Parallel Devices -- 7.2.3 Electro‐Thermal Network -- 7.2.4 Hardware Emulation Results -- 7.3 Physics‐Based Nonlinear IGBT/Diode Model -- 7.3.1 Physics‐Based Nonlinear p-i-n Diode Model -- 7.3.1.1 Model Formulation -- 7.3.1.2 Model Discretization and Linearization -- 7.3.1.3 Hardware Emulation on FPGA -- 7.3.2 Physics‐Based Nonlinear IGBT Model -- 7.3.2.1 Model Formulation -- 7.3.2.2 Model Discretization and Linearization -- 7.3.2.3 Hardware Emulation on FPGA -- 7.3.3 Hardware Emulation Results -- 7.3.3.1 Test circuit -- 7.3.3.2 Results and comparison -- 7.4 IGBT/Diode Curve‐Fitting Model -- 7.4.1 Linear Static Curve‐fitting Model -- 7.4.1.1 Static Characteristics -- 7.4.1.2 Switching Transients -- 7.4.2 Nonlinear Dynamic Curve‐fitting Model -- 7.4.3 Hardware Emulation Results -- 7.5 Summary -- Chapter 8 AC-DC Converters -- 8.1 Overview -- 8.2 Detailed Model -- 8.2.1 Detailed Equivalent Circuit Model -- 8.3 Equivalenced Device‐Level Model -- 8.3.1 Power Loss Calculation -- 8.3.2 Thermal Network Calculation -- 8.3.3 Hardware Emulation of SM Model on FPGA -- 8.3.4 MMC System Hardware Emulation -- 8.3.5 Real‐Time Emulation Results -- 8.3.5.1 Test Circuit and Hardware Resource Utilization -- 8.3.5.2 Results and Comparison for Single‐Phase Five‐Level MMC -- 8.3.5.3 Results for Three‐Phase Nine‐Level MMC -- 8.4 Virtual‐Line‐Partitioned Device‐Level Models -- 8.4.1 TLM‐Link Partitioning -- 8.4.2 Hardware Design on FPGA -- 8.4.2.1 Hardware Platform -- 8.4.2.2 Controller Emulation -- 8.4.2.3 MMC "]
[{"$nulls":4},"Emulation on FPGA -- 8.4.3 Real‐Time Emulation Results -- 8.4.3.1 MMC -- 8.4.3.2 Induction Machine Driven by Five‐Level MMC -- 8.5 MMC Partitioned by Coupled Voltage-Current Sources -- 8.5.1 V-I Coupling -- 8.5.2 Hardware Emulation Case of NBM‐Based MMC."]
[{"$nulls":4},"8.5.2.1 Power Converter HIL Emulation."]