{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":29,"n_cols":5,"rows_kept":29,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[10,2,10,3],[21,2,21,3],[22,2,22,3],[26,2,26,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910484388603321"]
[null,null,"Titolo",null,"Embedded Computer Systems: Architectures, Modeling, and Simulation : 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / / edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2009"]
[null,null,"ISBN",null,"1-282-33186-8"]
[{"$nulls":4},"9786612331862"]
[{"$nulls":4},"3-642-03138-2"]
[null,null,"Edizione",null,"[1st ed. 2009.]"]
[null,null,"Descrizione fisica",null,"1 online resource (354 p.)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 5657"]
[null,null,"Disciplina",null,"004.22"]
[null,null,"Soggetti",null,"Computer systems"]
[{"$nulls":4},"Computers"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Computer networks"]
[{"$nulls":4},"Electronic digital computers - Evaluation"]
[{"$nulls":4},"Computer System Implementation"]
[{"$nulls":4},"Computer Hardware"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"Computer Communication Networks"]
[{"$nulls":4},"System Performance and Evaluation"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Beachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of "]
[{"$nulls":4},"Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors — A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System."]
[null,null,null,"Sommario/riassunto","This book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009. The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on architectures for multimedia, multi/many cores architectures, VLSI architectures design, architecture modeling and exploration tools. In addition there are 14 papers from three special sessions which were organized on topics of current interest: instruction-set customization, reconfigurable computing and processor architectures, and mastering cell BE and GPU execution platforms."]