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[null,"1.","Record Nr.",null,"UNINA9910454505003321"]
[null,null,"Titolo",null,"Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]]"]
[null,null,"Pubbl/distr/stampa",null,"Cambridge : , : Cambridge University Press, , 2009"]
[null,null,"ISBN",null,"1-107-19643-4"]
[{"$nulls":4},"1-282-39124-0"]
[{"$nulls":4},"0-511-64683-6"]
[{"$nulls":4},"9786612391248"]
[{"$nulls":4},"0-511-62691-6"]
[{"$nulls":4},"0-511-57932-2"]
[{"$nulls":4},"0-511-65091-4"]
[{"$nulls":4},"0-511-57858-X"]
[{"$nulls":4},"0-511-58006-1"]
[null,null,"Descrizione fisica",null,"1 online resource (xi, 276 pages) : digital, PDF file(s)"]
[null,null,"Disciplina",null,"621.3815/48"]
[null,null,"Soggetti",null,"Integrated circuits - Verification"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Title from publisher's bibliographic system (viewed on 05 Oct 2015)."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references and index."]
[null,null,"Nota di contenuto",null,"Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva."]
[null,null,null,"Sommario/riassunto","Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of "]
[{"$nulls":4},"formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT)."]