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[null,"1.","Record Nr.",null,"UNINA9910451878903321"]
[null,null,"Titolo",null,"Communicating process architectures 2007 [[electronic resource] ] : WoTUG-30 : proceedings of the 30th WoTUG Technical Meeting, 8-11 July 2007, University of Surrey, Guildford, United Kingdom / / edited by Alistair A. McEwan ... [et al.]"]
[null,null,"Pubbl/distr/stampa",null,"Amsterdam ; Fairfax, VA, : IOS Press, 2007"]
[null,null,"ISBN",null,"6611029842"]
[{"$nulls":4},"1-281-02984-X"]
[{"$nulls":4},"9786611029845"]
[{"$nulls":4},"1-60750-261-5"]
[{"$nulls":4},"600-00-0368-4"]
[{"$nulls":4},"1-4356-0867-4"]
[null,null,"Descrizione fisica",null,"1 online resource (528 p.)"]
[null,null,"Collana",null,"Concurrent systems engineering series ; ; v. 65"]
[null,null,"Disciplina",null,"004"]
[null,null,"Soggetti",null,"Parallel processing (Electronic computers)"]
[{"$nulls":4},"occam (Computer program language)"]
[{"$nulls":4},"Transputers"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Electronic books."]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,"Nota di contenuto",null,"Title page; Preface; Programme Committee; Additional Reviewers; Contents; Fine-Grain Concurrency; Communicating Process Architecture for Multicores; Lazy Exploration and Checking of CSP Models with CSPsim; The Core Language of Aldwych; JCSProB: Implementing Integrated Formal Specifications in Concurrent Java; Components with Symbolic Transition Systems: A Java Implementation of Rendezvous; Concurrent/Reactive System Design with Honeysuckle; CSP and Real-Time: Reality or Illusion?; Testing and Sampling Parallel Systems; Mobility in JCSP: New Mobile Channel and Mobile Process Models"]
[{"$nulls":4},"C++CSP2: A Many-to-Many Threading Model for Multicore ArchitecturesDesign Principles of the SystemCSP Software Framework; PyCSP - Communicating Sequential Processes for Python; A Process-Oriented Architecture for Complex System Modelling; Concurrency "]
[{"$nulls":4},"Control and Recovery Management for Open e-Business Transactions; trancell - An Experimental ETC to Cell BE Translator; A Versatile Hardware-Software Platform for In-Situ Monitoring Systems; High Cohesion and Low Coupling: The Office Mapping Factor; A Process Oriented Approach to USB Driver Development"]
[{"$nulls":4},"A Native Transterpreter for the LEGO Mindstorms RCXIntegrating and Extending JCSP; Hardware/Software Synthesis and Verification Using Esterel; Modeling and Analysis of the AMBA Bus Using CSP and B; A Step Towards Refining and Translating B Control Annotations to Handel-C; Towards the Formal Verification of a Java Processor in Event-B; Advanced System Simulation, Emulation and Test (ASSET); Development of a Family of Multi-Core Devices Using Hierarchical Abstraction; Domain Specific Transformations for Hardware Ray Tracing"]
[{"$nulls":4},"A Reconfigurable System-on-Chip Architecture for Pico-Satellite MissionsTransactional CSP Processes; Algebras of Actions in Concurrent Processes; Using occam-pi Primitives with the Cell Broadband Engine; Shared-Memory Multi-Processor Scheduling Algorithms for CCSP; Compiling occam to C with Tock; Author Index"]
[null,null,null,"Sommario/riassunto","Deals with Computer Science and models of Concurrency. This title emphasizes on hardware/software co-design and the understanding of concurrency that results from these systems. It includes a range of papers on this topic, from the formal modeling of buses in co-design systems through to software simulation and development environments."]