{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":28,"n_cols":5,"rows_kept":28,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[22,2,22,3],[23,2,23,3],[25,2,25,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910409666503321"]
[null,null,"Autore",null,"Lutsyk Petro"]
[null,null,"Titolo",null,"A Pipelined Multi-Core Machine with Operating System Support : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020"]
[null,null,"ISBN",null,"3-030-43243-2"]
[null,null,"Edizione",null,"[1st ed. 2020.]"]
[null,null,"Descrizione fisica",null,"1 online resource (634 pages)"]
[null,null,"Collana",null,"Theoretical Computer Science and General Issues, , 2512-2029 ; ; 9999"]
[null,null,"Disciplina",null,"005.434"]
[null,null,"Soggetti",null,"Computer programming"]
[{"$nulls":4},"Computer engineering"]
[{"$nulls":4},"Computer networks"]
[{"$nulls":4},"Microprogramming"]
[{"$nulls":4},"Computer input-output equipment"]
[{"$nulls":4},"Logic programming"]
[{"$nulls":4},"Computer science"]
[{"$nulls":4},"Programming Techniques"]
[{"$nulls":4},"Computer Engineering and Networks"]
[{"$nulls":4},"Control Structures and Microprogramming"]
[{"$nulls":4},"Input/Output and Data Communications"]
[{"$nulls":4},"Logic in AI"]
[{"$nulls":4},"Theory of Computation"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,"Nota di contenuto",null,"Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic."]
[null,null,null,"Sommario/riassunto","This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive "]
[{"$nulls":4},"operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk ."]