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[null,"1.","Record Nr.",null,"UNINA9910299760103321"]
[null,null,"Autore",null,"Mehta Ashok B"]
[null,null,"Titolo",null,"System Verilog assertions and functional coverage : guide to language, methodology and applications / / Ashok B. Mehta"]
[null,null,"Pubbl/distr/stampa",null,"New York, : Springer, c2014"]
[null,null,"ISBN",null,"1-4614-7324-1"]
[null,null,"Descrizione fisica",null,"1 online resource (xxxiii, 356 pages) : illustrations (some color)"]
[null,null,"Collana",null,"Gale eBooks"]
[null,null,"Disciplina",null,"004.1"]
[{"$nulls":4},"620"]
[{"$nulls":4},"621.381"]
[{"$nulls":4},"621.3815"]
[null,null,"Soggetti",null,"Computer hardware description languages"]
[{"$nulls":4},"Verilog (Computer hardware description language)"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Includes index."]
[null,null,"Nota di contenuto",null,"Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert).- Sampled Value Functions   $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material)."]
[null,null,null,"Sommario/riassunto","This book provides a hands-on, application-oriented guide to the language and methodology of both System Verilog Assertions and System Verilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.  Written by a professional end-user of both System Verilog Assertions and System Verilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of "]
[{"$nulls":4},"complex checkers for functional verification, thereby reducing drastically their time to design and debug. Covers both System Verilog Assertions and System Verilog Functional Coverage language and methodologies; Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example; Includes practical labs that enable readers to put in practice the concepts explained in the book."]