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[null,"1.","Record Nr.",null,"UNINA9910299681603321"]
[null,null,"Titolo",null,"More than Moore Technologies for Next Generation Computer Design / / edited by Rasit O. Topaloglu"]
[null,null,"Pubbl/distr/stampa",null,"New York, NY : , : Springer New York : , : Imprint : Springer, , 2015"]
[null,null,"ISBN",null,"1-4939-2163-0"]
[null,null,"Edizione",null,"[1st ed. 2015.]"]
[null,null,"Descrizione fisica",null,"1 online resource (225 p.)"]
[null,null,"Disciplina",null,"004.1"]
[{"$nulls":4},"620"]
[{"$nulls":4},"621.381"]
[{"$nulls":4},"621.3815"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Electronics"]
[{"$nulls":4},"Microelectronics"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Circuits and Systems"]
[{"$nulls":4},"Electronics and Microelectronics, Instrumentation"]
[{"$nulls":4},"Processor Architectures"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references."]
[null,null,"Nota di contenuto",null,"Impact of TSV and Device Scaling on the Quality of 3D Ics -- 3D Integration Technology -- Design and Optimization of Spin-Transfer Torque MRAMs -- Embedded STT-MRAM: Device and Design -- A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis -- Nano-Photonic Networks-on-Chip for Future Chip Multiprocessors -- Design Automation for On-chip Nanophotonic Integration."]
[null,null,null,"Sommario/riassunto","This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance.  Authors discuss in detail what are known commonly as “More than Moore” (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to “Moore's Law”.  Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect."]