{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":1,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":24,"n_cols":5,"rows_kept":24,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[2,4,2,5],[3,2,3,3],[4,2,4,3],[5,2,5,3],[6,2,6,3],[7,2,7,3],[8,2,8,3],[9,2,9,3],[16,2,16,3],[17,2,17,3],[21,2,21,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNINA9910254182703321"]
[null,null,"Autore",null,"Mohamed Khaled Salah"]
[null,null,"Titolo",null,"IP Cores Design from Specifications to Production : Modeling, Verification, Optimization, and Protection / / by Khaled Salah Mohamed"]
[null,null,"Pubbl/distr/stampa",null,"Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016"]
[null,null,"ISBN",null,"3-319-22035-7"]
[null,null,"Edizione",null,"[1st ed. 2016.]"]
[null,null,"Descrizione fisica",null,"1 online resource (162 p.)"]
[null,null,"Collana",null,"Analog Circuits and Signal Processing, , 2197-1854"]
[null,null,"Disciplina",null,"620"]
[null,null,"Soggetti",null,"Electronic circuits"]
[{"$nulls":4},"Microprocessors"]
[{"$nulls":4},"Computer architecture"]
[{"$nulls":4},"Electronics"]
[{"$nulls":4},"Electronic Circuits and Systems"]
[{"$nulls":4},"Processor Architectures"]
[{"$nulls":4},"Electronics and Microelectronics, Instrumentation"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Description based upon print version of record."]
[null,null,null,"Nota di bibliografia","Includes bibliographical references at the end of each chapters."]
[null,null,"Nota di contenuto",null,"1. Introduction -- 2. IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection -- 3. Analyzing the Trade-off between Different Memory Cores and Controllers -- 4. SOC BUSES AND PERIPHERALS: FEATURES AND ARCHITECTURES -- 5. Verilog for Implementation and Verification -- 6. New Trends in SoC Verification: UVM, Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation -- 7. Conclusions."]
[null,null,null,"Sommario/riassunto","This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including  those associated with many of the most common memory cores, controller IPs  and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain.  A SoC case study is presented to compare traditional verification with the new verification methodologies. ·         Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection; ·         Introduce a deep introduction for Verilog for both implementation and verification "]
[{"$nulls":4},"point of view.  ·         Demonstrates how to use IP in applications such as memory controllers and SoC buses. ·         Describes a new verification methodology called bug localization; ·         Presents a novel scan-chain methodology for RTL debugging; ·         Enables readers to employ UVM methodology in straightforward, practical terms."]