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[null,"1.","Record Nr.",null,"UNINA9910146730503321"]
[null,null,"Titolo",null,"2007 IEEE International Conf on Application-specific Systems, Architectures and Processors (ASAP)"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : IEEE, 2007"]
[null,null,"ISBN",null,"9781509088706"]
[{"$nulls":4},"1509088709"]
[null,null,"Descrizione fisica",null,"1 online resource"]
[null,null,"Disciplina",null,"004.16"]
[null,null,"Soggetti",null,"Array processors"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Sommario/riassunto","The Logarithmic Number System (LNS) makes multiplication, division and powering easy, but subtraction is expensive. Cotransformation converts the difficult operation of logarithmic subtraction into the easier operation of logarithmic addition. In this paper, a new variant of cotransformation is proposed, which is simpler to design and more economical in hardware than previous cotransformation methods. The novel method commutes operands differently for addition than for subtraction. Simulation results show how many guard bits are required by the new cotransformation to guarantee faithful rounding and that, even without guard bits, cotransformation produces an LNS unit more accurate than a previously published Hardware-Description-Language (HDL) library for LNS arithmetic that uses only multipartite tables or 2nd-order interpolation."]