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[null,"1.","Record Nr.",null,"UNINA9910145114803321"]
[null,null,"Titolo",null,"2007 European Conference on Circuit Theory and Design"]
[null,null,"Pubbl/distr/stampa",null,"[Place of publication not identified], : I E E E, 2007"]
[null,null,"ISBN",null,"9781509086498"]
[{"$nulls":4},"1509086498"]
[{"$nulls":4},"9781424413423"]
[{"$nulls":4},"1424413427"]
[null,null,"Descrizione fisica",null,"1 online resource"]
[null,null,"Disciplina",null,"621.3192"]
[null,null,"Soggetti",null,"Electric circuits"]
[{"$nulls":4},"Electric filters"]
[{"$nulls":4},"Electric networks"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Sommario/riassunto","3D discrete wavelet transform (DWT) is a compute-intensive task that is usually implemented on specific architectures in many real-time medical imaging systems. In this paper, a novel area-efficient high-throughput 3D DWT architecture is proposed based on distributed arithmetic. A tap-merging technique is used to reduce the size of DA lookup tables. The proposed architectures were designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The synthesis results show the proposed architecture has a low area cost and can run up to 85 MHz, which can perform a five-level 3D wavelet analysis for seven 128 times 128 times 128 volume images per second."]