{"text_format":"2","workbook":"xls","n_sheets":1,"sheets":["report2"],"not_rendered":{"charts":0,"images":0,"macros":0,"external_links":1,"defined_names":2,"comments":0,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"run_cost":"one","rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900","formulas":"cached_only"}

{"sheet":"report2","index":0,"n_rows":44,"n_cols":5,"rows_kept":44,"cut":false,"hidden":false,"merged":[[0,2,0,3],[0,4,0,5],[1,2,1,3],[1,4,1,5],[2,2,2,3],[3,2,3,3],[4,2,4,3],[9,2,9,3],[10,2,10,3],[13,2,13,3],[13,4,13,5],[14,2,14,3],[14,4,14,5],[15,2,15,3],[16,2,16,3],[17,2,17,3],[18,2,18,3],[19,2,19,3],[20,2,20,3],[21,2,21,3],[34,2,34,3],[35,2,35,3],[39,2,39,3]],"flags":["formulas_cached_only"]}
[null,"1.","Record Nr.",null,"UNISA996321304503316"]
[null,null,"Titolo",null,"Academia : arkhitektura i stroitelʹstvo"]
[null,null,"Pubbl/distr/stampa",null,"Moskva : , : Rossiĭskai͡a akademii͡a arkhitektury i stroitelʹnykh nauk"]
[null,null,"Descrizione fisica",null,"1 online resource"]
[null,null,"Soggetti",null,"Architecture"]
[{"$nulls":4},"Architecture - Russia (Federation)"]
[{"$nulls":4},"Building"]
[{"$nulls":4},"Periodicals."]
[{"$nulls":4},"Russia (Federation)"]
[null,null,"Lingua di pubblicazione",null,"Russo"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Periodico"]
[null,null,null,"Note generali","Refereed/Peer-reviewed"]
[null,"2.","Record Nr.",null,"UNINA9910143633803321"]
[null,null,"Titolo",null,"Parallel and Distributed Processing : 15 IPDPS 2000 Workshops Cancun, Mexico, May 1–5, 2000 Proceedings / / edited by Jose Rolim"]
[null,null,"Pubbl/distr/stampa",null,"Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2000"]
[null,null,"ISBN",null,"3-540-45591-4"]
[null,null,"Edizione",null,"[1st ed. 2000.]"]
[null,null,"Descrizione fisica",null,"1 online resource (DCL, 667 p. 370 illus. in color.)"]
[null,null,"Collana",null,"Lecture Notes in Computer Science, , 1611-3349 ; ; 1800"]
[null,null,"Disciplina",null,"004.36"]
[null,null,"Soggetti",null,"Computer systems"]
[{"$nulls":4},"Software engineering"]
[{"$nulls":4},"Computer engineering"]
[{"$nulls":4},"Computer networks"]
[{"$nulls":4},"Computer science"]
[{"$nulls":4},"Computer science - Mathematics"]
[{"$nulls":4},"Mathematics - Data processing"]
[{"$nulls":4},"Computer System Implementation"]
[{"$nulls":4},"Software Engineering"]
[{"$nulls":4},"Computer Engineering and Networks"]
[{"$nulls":4},"Theory of Computation"]
[{"$nulls":4},"Mathematics of Computing"]
[{"$nulls":4},"Computational Mathematics and Numerical Analysis"]
[null,null,"Lingua di pubblicazione",null,"Inglese"]
[null,null,"Formato",null,"Materiale a stampa"]
[null,null,null,"Livello bibliografico","Monografia"]
[null,null,null,"Note generali","Bibliographic Level Mode of Issuance: Monograph"]
[null,null,null,"Nota di bibliografia","Includes bibliographical references at the end of each chapters and index."]
[null,null,"Nota di contenuto",null,"3rd Workshop on Personal Computer based Networks Of Workstations (PC-NOW 2000) -- Memory Management in a combined VIA/SCI Hardware -- ATOLL, a new switched, high speed Interconnect in Comparison to Myrinet and SCI -- ClusterNet: An Object-Oriented Cluster Network -- GigaBit Performance under NT -- MPI Collective Operations over IP Multicast -- An Open Market-Based Architecture for Distributed Computing -- The MultiCluster Model to the Integrated Use of Multiple Workstation Clusters -- Parallel Information Retrieval on an SCI-Based PC-NOW -- A PC-NOW Based Parallel Extension for a Sequential DBMS -- Workshop on Advances in Parallel and Distributed Computational Models -- The Heterogeneous Bulk Synchronous Parallel "]
[{"$nulls":4},"Model -- On stalling in LogP -- Parallelizability of some P-complete problems -- A New Computation of Shape Moments via Quadtree Decomposition -- The Fuzzy Philosophers -- A Java Applet to Visualize Algorithms on Reconfigurable Mesh -- A Hardware Implementation of PRAM and its Performance Evaluation -- A Non-Binary Parallel Arithmetic Architecture -- Multithreaded Parallel Computer Model with Performance Evaluation -- Workshop on Parallel and Distributed Computing in Image Processing, Video Processing, and Multimedia (PDIVM 2000) -- MAJC-5200: A High Performance Microprocessor for Multimedia Computing -- A Novel Superscalar Architecture for Fast DCT Implementation -- Computing Distance Maps Efficiently Using An Optical Bus -- Advanced Data Layout Optimization for Multimedia Applications -- Parallel Parsing of MPEG Video in a Multi-threaded Multiprocessor Environment -- Parallelization Techniques for Spatial-Temporal Occupancy Maps from Multiple Video Streams -- Heuristic Solutions for a Mapping Problem in a TV-Anytime Server Network -- RPV: A Programming Environment for Real-time ParallelVision —Specification and programming methodology— -- Parallel low-level image processing on a distributed-memory system -- Congestion-free Routing of Streaming Multimedia Content in BMIN-based Parallel Systems -- Performance of On-Chip Multiprocessors for Vision Tasks (Summary) -- Parallel Hardware-Software Architecture for computation of Discrete Wavelet Transform using the Recursive Merge Filtering algorithm -- Fifth International Workshop on High-level Parallel Programming Models and Supportive Environments HIPS 2000 -- Pipelining Wavefront Computations: Experiences and Performance -- Specification Techniques for Automatic Performance Analysis Tools -- PDRS: A Performance Data Representation System -- Clix — A Hybrid Programming Environment for Distributed Objects and Distributed Shared Memory -- Controlling Distributed Shared Memory Consistency from High Level Programming Languages -- Online Computation of Critical Paths for Multithreaded Languages -- Problem Solving Environment Infrastructure for High Performance Computer Systems -- Combining Fusion Optimizations and Piecewise Execution of Nested Data-Parallel Programs -- Declarative concurrency in Java -- Scalable Monitoring Technique for Detecting Races in Parallel Programs -- 3rd IPDPS Workshop on High Performance Data Mining -- Implementation Issues in the Design of I/O Intensive Data Mining Applications on Clusters of Workstations -- A Requirements Analysis for Parallel KDD Systems -- Parallel Data Mining on ATM-Connected PC Cluster and Optimization of its Execution Environments -- The Parallelization of a Knowledge Discovery System with Hypergraph Representation -- Parallelisation of C4.5 as a Particular Divide and Conquer Computation -- Scalable Parallel Clustering for Data Mining on Multicomputers -- Exploiting DatasetSimilarity for Distributed Mining -- Scalable Model for Extensional and Intensional Descriptions of Unclassified Data -- Parallel Data Mining of Bayesian Networks from Telecommunications Network Data -- Irregular’00 Seventh International Workshop on Solving Irregularly Structured Problems in Parallel -- Load Balancing and Continuous Quadratic Programming -- Parallel Management of Large Dynamic Shared Memory Space: A Hierarchical FEM Application -- Efficient Parallelization of Unstructured Reductions on Shared Memory Parallel Architectures -- Parallel FEM Simulation of Crack Propagation — Challenges, Status, and Perspectives -- Support for Irregular Computations in Massively Parallel PIM Arrays, Using an Object-Based Execution Model -- Executing Communication-Intensive Irregular Programs Efficiently -- Non-Memory-Based and Real-Time Zerotree Building for Wavelet Zerotree Coding Systems -- Graph "]
[{"$nulls":4},"Partitioning for Dynamic, Adaptive and Multi-phase Computations -- A Multilevel Algorithm for Spectral Partitioning with Extended Eigen-Models -- An Integrated Decomposition and Partitioning Approach for Irregular Block-Structured Applications -- Ordering Unstructured Meshes for Sparse Matrix Computations on Leading Parallel Systems -- A GRASP for computing approximate solutions for the Three-Index Assignment Problem -- On Identifying Strongly Connected Components in Parallel -- A Parallel, Adaptive Refinement Scheme for Tetrahedral and Triangular Grids -- PaStiX: A Parallel Sparse Direct Solver Based on a Static Scheduling for Mixed 1D/2D Block Distributions -- Workshop on Java for Parallel and Distributed Computing -- An IP Next Generation Compliant Java™ Virtual Machine -- An Approach to Asynchronous Object-Oriented Parallel and Distributed Computing on Wide-Area Systems -- Performance Issuesfor Multi-language Java Applications -- MPJ: A Proposed Java Message Passing API and Environment for High Performance Computing -- Implementing Java consistency using a generic, multithreaded DSM runtime system -- Third Workshop on Bio-Inspired Solutions to Parallel Processing Problems (BioSP3) -- Take Advantage of the Computing Power of DNA Computers -- Agent surgery: The case for mutable agents -- Was Collective Intelligence1 before Life on Earth? -- Solving Problems on Parallel Computers by Cellular Programming -- Multiprocessor Scheduling with Support by Genetic Algorithms - based Learning Classifier System -- Viewing Scheduling Problems through Genetic and Evolutionary Algorithms -- Dynamic Load Balancing Model: Preliminary Assessment of a Biological Model for a Pseudo-Search Engine -- A Parallel Co-evolutionary Metaheuristic -- Neural Fraud Detection in Mobile Phone Operations -- Information Exchange in Multi Colony Ant Algorithms -- A Surface-Based DNA Algorithm for the Expansion of Symbolic Determinants -- Hardware Support for Simulated Annealing and Tabu Search -- Eighth International Workshop on Parallel and Distributed Real-Time Systems -- A Distributed Real Time Coordination Protocol -- A Segmented Backup Scheme for Dependable Real Time Communication in Multihop Networks -- Real-Time Coordination in Distributed Multimedia Systems -- Supporting Fault-Tolerant Real-Time Applications using the RED-Linux General Scheduling Framework -- Are COTS suitable for building distributed fault-tolerant hard real-time systems? -- Autonomous Consistency Technique in Distributed Database with Heterogeneous Requirements -- Real-time Transaction Processing Using Two-stage Validation in Broadcast Disks -- Using Logs to Increase Availability in Real-Time Main-Memory Database -- Components are from Mars -- 2 + 10 ? 1 + 50 ! -- A Framework for Embedded Real-time System Design -- Best-effort Scheduling of (m,k)-firm Real-time Streams in Multihop Networks -- Predictability and Resource Management in Distributed Multimedia Presentations -- Quality of Service Negotiation for Distributed, Dynamic Real-time Systems -- An Open Framework for Real-Time Scheduling Simulation -- 5th International Workshop on Embedded/Distributed HPC Systems and Applications (EHPC 2000) -- A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA -- Application Challenges: System Health Management for Complex Systems -- Accommodating QoS Prediction in an Adaptive Resource Management Framework -- Network Load Monitoring in Distributed Systems -- A Novel Specification and Design Methodology Of Embedded Multiprocessor Signal Processing Systems Using High-Performance Middleware -- Auto Source Code Generation and Run-Time Infrastructure and Environment for High Performance, Distributed Computing Systems -- Developing an Open Architecture for Performance Data Mining -- A 90k gate “CLB” for "]
[{"$nulls":4},"Parallel Distributed Computing -- Power-Aware Replication of Data Structures in Distributed Embedded Real-Time Systems -- Comparison of MPI Implementations on a Shared Memory Machine -- A Genetic Algorithm Approach to Scheduling Communications for a Class of Parallel Space-Time Adaptive Processing Algorithms -- Reconfigurable Parallel Sorting and Load Balancing on a Beowulf Cluster: HeteroSort -- 7th Reconfigurable Architectures Workshop (RAW 2000) -- Run-Time Reconfiguration at Xilinx (invited talk) -- JRoute: A Run-Time Routing API for FPGA Hardware -- A Reconfigurable Content Addressable Memory -- ATLANTIS — A Hybrid FPGA/RISC Based Re-configurable System -- The Cellular Processor Architecture CEPRA-1X and itsConfiguration by CDL -- Loop Pipelining and Optimization for Run Time Reconfiguration -- Compiling Process Algebraic Descriptions into Reconfigurable Logic -- Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints -- Module Allocation for Dynamically Reconfigurable Systems -- Augmenting Modern Superscalar Architectures with Configurable Extended Instructions -- Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping -- Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation -- Constan t-Time Hough Transform On A 3D Reconfigurable Mesh Using Fewer Processors -- Fifth International Workshop on Formal Methods for Parallel Programming: Theory and Applications FMPPTA 2000 -- A Method for Automatic Cryptographic Protocol Verification -- Verification Methods ."]
[null,null,null,"Sommario/riassunto","This volume contains the proceedings from the workshops held in conjunction with the IEEE International Parallel and Distributed Processing Symposium, IPDPS 2000, on 1-5 May 2000 in Cancun, Mexico. The workshopsprovidea forum for bringing together researchers,practiti- ers, and designers from various backgrounds to discuss the state of the art in parallelism.Theyfocusondi erentaspectsofparallelism,fromruntimesystems to formal methods, from optics to irregular problems, from biology to networks of personal computers, from embedded systems to programming environments; the following workshops are represented in this volume: { Workshop on Personal Computer Based Networks of Workstations { Workshop on Advances in Parallel and Distributed Computational Models { Workshop on Par. and Dist. Comp. in Image, Video, and Multimedia { Workshop on High-Level Parallel Prog. Models and Supportive Env. { Workshop on High Performance Data Mining { Workshop on Solving Irregularly Structured Problems in Parallel { Workshop on Java for Parallel and Distributed Computing { WorkshoponBiologicallyInspiredSolutionsto ParallelProcessingProblems { Workshop on Parallel and Distributed Real-Time Systems { Workshop on Embedded HPC Systems and Applications { Recon gurable Architectures Workshop { Workshop on Formal Methods for Parallel Programming { Workshop on Optics and Computer Science { Workshop on Run-Time Systems for Parallel Programming { Workshop on Fault-Tolerant Parallel and Distributed Systems All papers published in the workshops proceedings were selected by the p- gram committee on the basis of referee reports. Each paper was reviewed by independent referees who judged the papers for originality, quality, and cons- tency with the themes of the workshops."]